ADSP-BF525KBCZ-6(RevPrG) 查看數據表（PDF） - Analog Devices

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ADSP-BF525KBCZ-6
(Rev.:RevPrG)

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are members of the Blackfin family of products,

incorporating the Analog Devices/Intel Micro Signal Architec-

ture (MSA). Blackfin processors combine a dual-MAC state-of-

the-art signal processing engine, the advantages of a clean,

orthogonal RISC-like microprocessor instruction set, and sin-

gle-instruction, multiple-data (SIMD) multimedia capabilities

into a single instruction-set architecture.

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are completely code compatible with other Blackfin

processors. The ADSP-BF523/525/527 processors offer perfor-

mance up to 600 MHz. The ADSP-BF522/524/526 processors

offer performance up to 400 MHz and reduced static power

consumption. Differences with respect to peripheral combina-

tions are shown in Table 1.

Table 1. Processor Comparison

Feature

Host DMA

111111

USB

–11–11

Ethernet MAC

––1––1

Internal Voltage Regulator

–––111

TWI

111111

SPORTs

222222

UARTs

222222

SPI

111111

GP Timers

888888

Watchdog Timers

111111

RTC

111111

Parallel Peripheral Interface 1 1 1 1 1 1

GPIOs

48 48 48 48 48 48

L1 Instruction SRAM

48K 48K 48K 48K 48K 48K

L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K

L1 Data SRAM

32K 32K 32K 32K 32K 32K

L1 Data SRAM/Cache

32K 32K 32K 32K 32K 32K

L1 Scratchpad

4K 4K 4K 4K 4K 4K

L3 Boot ROM

Maximum Speed Grade1

32K 32K 32K 32K 32K 32K

400 MHz 600 MHz

Maximum System Clock Speed 80 MHz 133 MHz

Package Options

289-Ball CSP_BGA

208-Ball CSP_BGA

1 Maximum speed grade is not available with every possible SCLK selection.

ADSP-BF522/523/524/525/526/527

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which is the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. This capability can result in a substantial reduc-

tion in power consumption, compared with just varying the

frequency of operation. This allows longer battery life for

portable appliances.

SYSTEM INTEGRATION

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are highly integrated system-on-a-chip solutions for the

next generation of embedded network connected applications.

By combining industry-standard interfaces with a high perfor-

mance signal processing core, cost-effective applications can be

developed quickly, without the need for costly external compo-

nents. The system peripherals include an IEEE-compliant 802.3

10/100 Ethernet MAC, a USB 2.0 high speed OTG controller, a

TWI controller, a NAND flash controller, two UART ports, an

SPI port, two serial ports (SPORTs), eight general purpose 32-

bit timers with PWM capability, a core timer, a real-time clock,

a watchdog timer, a Host DMA (HOSTDP) interface, and a par-

allel peripheral interface (PPI).

PROCESSOR PERIPHERALS

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors contain a rich set of peripherals connected to the core via

several high bandwidth buses, providing flexibility in system

configuration as well as excellent overall system performance

(see the block diagram on Page 1). These Blackfin processors

contain dedicated network communication modules and high

speed serial and parallel ports, an interrupt controller for flexi-

ble management of interrupts from the on-chip peripherals or

external sources, and power management control functions to

tailor the performance and power characteristics of the proces-

sor and system to many application scenarios.

All of the peripherals, except for the general-purpose I/O, TWI,

real-time clock, and timers, are supported by a flexible DMA

structure. There are also separate memory DMA channels dedi-

cated to data transfers between the processor's various memory

spaces, including external SDRAM and asynchronous memory.

Multiple on-chip buses running at up to 133 MHz provide

enough bandwidth to keep the processor core running along

with activity on all of the on-chip and external peripherals.

Rev. PrG | Page 3 of 80 | February 2009

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