ADSP-BF526(RevPrG) 查看數據表（PDF） - Analog Devices
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ADSP-BF526 Datasheet PDF : 80 Pages
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ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
Table 3. System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event
DMA10 Channel (UART1 RX)
DMA11 Channel (UART1 TX)
OTP Memory Interrupt
GP Counter
DMA1 Channel (MAC RX/HOSTDP)
Port H Interrupt A
DMA2 Channel (MAC TX/NFC)
Port H Interrupt B
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port G Interrupt A
Port G Interrupt B
MDMA Stream 0
MDMA Stream 1
Software Watchdog Timer
Port F Interrupt A
Port F Interrupt B
SPI Status
NFC Status
HOSTDP Status
Host Read Done
USB_EINT Interrupt
USB_INT0 Interrupt
USB_INT1 Interrupt
USB_INT2 Interrupt
USB_DMAINT Interrupt
General Purpose
Default
Interrupt (at RESET) Peripheral Interrupt ID Core Interrupt ID SIC Registers
IVG10
24
3
IAR3 IMASK0, ISR0, IWR0
IVG10
25
3
IAR3 IMASK0, ISR0, IWR0
IVG11
26
4
IAR3 IMASK0, ISR0, IWR0
IVG11
27
4
IAR3 IMASK0, ISR0, IWR0
IVG11
28
4
IAR3 IMASK0, ISR0, IWR0
IVG11
29
4
IAR3 IMASK0, ISR0, IWR0
IVG11
30
4
IAR3 IMASK0, ISR0, IWR0
IVG11
31
4
IAR3 IMASK0, ISR0, IWR0
IVG12
32
5
IAR4 IMASK1, ISR1, IWR1
IVG12
33
5
IAR4 IMASK1, ISR1, IWR1
IVG12
34
5
IAR4 IMASK1, ISR1, IWR1
IVG12
35
5
IAR4 IMASK1, ISR1, IWR1
IVG12
36
5
IAR4 IMASK1, ISR1, IWR1
IVG12
37
5
IAR4 IMASK1, ISR1, IWR1
IVG12
38
5
IAR4 IMASK1, ISR1, IWR1
IVG12
39
5
IAR4 IMASK1, ISR1, IWR1
IVG12
40
5
IAR5 IMASK1, ISR1, IWR1
IVG12
41
5
IAR5 IMASK1, ISR1, IWR1
IVG13
42
6
IAR5 IMASK1, ISR1, IWR1
IVG13
43
6
IAR5 IMASK1, ISR1, IWR1
IVG13
44
6
IAR5 IMASK1, ISR1, IWR1
IVG13
45
6
IAR5 IMASK1, ISR1, IWR1
IVG13
46
6
IAR5 IMASK1, ISR1, IWR1
IVG7
47
0
IAR5 IMASK1, ISR1, IWR1
IVG7
48
0
IAR6 IMASK1, ISR1, IWR1
IVG7
49
0
IAR6 IMASK1, ISR1, IWR1
IVG7
50
0
IAR6 IMASK1, ISR1, IWR1
IVG10
51
3
IAR6 IMASK1, ISR1, IWR1
IVG10
52
3
IAR6 IMASK1, ISR1, IWR1
IVG10
53
3
IAR6 IMASK1, ISR1, IWR1
IVG10
54
3
IAR6 IMASK1, ISR1, IWR1
IVG10
55
3
IAR6 IMASK1, ISR1, IWR1
Event Control
The processor provides a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 16 bits wide.
• CEC interrupt latch register (ILAT) – Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be writ-
ten only when its corresponding IMASK bit is cleared.
• CEC interrupt mask register (IMASK) – Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-pur-
pose interrupts can be globally enabled and disabled with
the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
Rev. PrG | Page 8 of 80 | February 2009
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