ADT7463 查看數據表（PDF） - ON Semiconductor
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ADT7463 Datasheet PDF : 52 Pages
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ADT7463
Parameter
Min
Typ Max Unit
DIGITAL INPUT LOGIC LEVELS
(TACH INPUTS)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
2.0
V
5.5
V
+0.8 V
–0.3
V
0.5
V p-p
DIGITAL INPUT LOGIC LEVELS
(THERM) AGTL+
Input High Voltage, VIH
Input Low Voltage, VIL
0.75 � VCCP
V
0.4
V
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
–1
µA
+1
µA
5
pF
SERIAL BUS TIMING5
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
1.3
Start Setup Time, tSU;STA
0.6
Start Hold Time, tHD;STA
0.6
SCL Low Time, tLOW
1.3
SCL High Time, tHIGH
0.6
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
100
Data Hold Time, tHD;DAT
300
Detect Clock Low Timeout, tTIMEOUT
15
400
kHz
50
ns
µs
µs
µs
µs
50
µs
1000 ns
300
µs
ns
ns
35
ms
NOTES
1All voltages are measured with respect to GND, unless otherwise specified.
2Typicals are at TA = 25°C and represent the most likely parametric norm.
3Logic inputs accept input high voltages up to VMAX even when the device is operating down to VMIN.
4Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
5Guaranteed by design, not production tested.
Specifications subject to change without notice.
Test Conditions/Comment
Maximum Input Voltage
Minimum Input Voltage
VIN = VCC
VIN = 0
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
Can Be Optionally Disabled
tR
tF
tLOW
tHD;STA
SCL
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
SDA
tBUF
S
P
S
Figure 1. Diagram for Serial Bus Timing
tSU;STO
P
REV. C
Rev. 4 | Page 3 of 52 | www.onsemi.com
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