ADT7476AARQZ-REEL 查看數據表（PDF） - Analog Devices
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ADT7476AARQZ-REEL Datasheet PDF : 72 Pages
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ADT7476A
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Detect Clock Low Timeout, tTIMEOUT
Min
Typ
Max
Unit
Test Conditions/Comments
2.0
5.5
0.8
−0.3
0.5
V
V
V
V
V p-p
Maximum input voltage
Minimum input voltage
0.75 × VCC V
0.4
V
±1
μA
VIN = VCC
±1
μA
VIN = 0
5
pF
See Figure 2
10
400
kHz
50
ns
4.7
μs
4.7
μs
4.0
50
μs
1,000
ns
300
μs
250
ns
15
35
ms
Can be optionally disabled
1 All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and probably represent a parametric norm. Logic inputs
accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge,
and VIH = 2.0 V for a rising edge.
2 SMBus timing specifications are guaranteed by design and are not production tested.
SCL
tR
tLOW
tHD; STA
SDA
tBUF
P
S
tHD; DAT
tF
tHIGH
tSU; DAT
tHD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
Rev. 0 | Page 4 of 72
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