EVAL-ADT7490EBZ 查看數據表（PDF） - Analog Devices
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EVAL-ADT7490EBZ Datasheet PDF : 76 Pages
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ADT7490
Parameter
Min
Typ
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
0.1
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Hysteresis
500
Digital I/O (PECI PIN)1
0.95
VTT, Supply Voltage
Input High Voltage , VIH
0.55 × VTT2
Input Low Voltage, VIL
Hysteresis1
0.1 × VTT2
High Level Output Source Current, ISOURCE
Low Level Output Sink Current, ISINK
0.5
Signal Noise Immunity, VNOISE
300
DIGITAL INPUT LOGIC LEVELS (TACH1 to
TACH3)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM)
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING1
Clock Frequency, fSCLK
Glitch Immunity, tSW
Bus Free Time, tBUF
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Detect Clock Low Timeout, tTIMEOUT
−0.3
0.5
±1
±1
5
10
4.7
4.7
4.0
250
15
Max
Unit
Test Conditions/Comments
0.4
V
IOUT = −4.0 mA
1.0
μA
VOUT = VCC
V
0.4
V
mV
1.26
V
0.5 × VTT2
6
1.0
V
V
mV
mA
mA
mV p-p
Hysteresis between input switching levels
VOH = 0.75 × VTT
VOL = 0.25 × VTT
Noise glitches from 10 MHz to 100 MHz,
width up to 50 ns
V
5.5
V
0.8
V
V
V p-p
0.75 × VCC V
0.4
V
μA
μA
pF
400
kHz
50
ns
μs
μs
50
μs
1000
ns
300
μs
ns
35
ms
Maximum input voltage
Minimum input voltage
VIN = VCC
VIN = 0
See Figure 2
Can be optionally disabled
1 Guaranteed by design, not production tested.
2 VTT is the voltage input on Pin 8. The VTT voltage is determined by the processor installed on the system.
tR
tF
tLOW
SCL
tHD;STA
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
SDA
tBUF
P
S
S
P
Figure 2. SMBus Timing Diagram
Rev. 0 | Page 5 of 76
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