ADT7473 查看數據表（PDF） - ON Semiconductor
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ADT7473 Datasheet PDF : 74 Pages
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ADT7473
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
Digital Input Logic Levels (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Voltage, VIH
Input Low Voltage, VIL
Input Low Current, IIL
Input Capacitance, CIN
Serial Bus Timing (Note 2)
VIN = VCC
VIN = 0
(See Figure 2)
0.75 x VCC
V
0.8
V
±1
mA
±1
mA
5.0
pF
Clock Frequency, fSCLK
10
400
kHz
Glitch Immunity, tSW
50
ns
Bus Free Time, tBUF
4.7
ms
SCL Low Time, tLOW
4.7
ms
SCL High Time, tHIGH
4.0
50
ms
SCL, SDA Rise Time, tr
1,000
ns
SCL, SDA Fall Time, tf
300
ms
Data Setup Time, tSU; DAT
250
ns
Detect Clock Low Timeout, tTIMEOUT
Can be optionally disabled
15
35
ms
1. All voltages are measured with respect to GND, unless otherwise noted. Typicals are at TA = 25°C and represent most likely parametric norm.
Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic
levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
2. Serial management bus (SMBus) timing specifications are guaranteed by design and are not production tested.
SCL
tLOW tR
tHD: STA
tHD: DAT
tF
tHIGH
tSU: DAT
tHD: STA
tSU: STA
SDA
tBUF
S
P
S
Figure 2. Serial Bus Timing Diagram
tSU: STO
P
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