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ADT7475 查看數據表(PDF) - ON Semiconductor

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ADT7475 Datasheet PDF : 58 Pages
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ADT7475
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
Power Supply
Supply Voltage
3.0
3.3
3.6
V
Supply Current, ICC
TemperaturetoDigital Converter
Interface inactive, ADC active
1.5
3.0
mA
Local Sensor Accuracy
Resolution
0°C TA 85°C
40°C TA +125°C
±0.5
±1.5
°C
±2.5
0.25
Remote Diode Sensor Accuracy
Resolution
0°C TA 85°C
40°C TA +125°C
±0.5
1.5
°C
±2.5
0.25
Remote Sensor Source Current
High level
Low level
180
mA
11
ANALOGTODIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error (TUE)
Differential Nonlinearity (DNL)
Power Supply Sensitivity
8 bits
±1.5
%
±1
LSB
±0.1
%/V
Conversion Time (Voltage Input)
Conversion Time (Local Temperature)
Conversion Time (Remote Temperature)
Total Monitoring Cycle Time
Averaging enabled
Averaging enabled
Averaging enabled
Averaging enabled
Averaging disabled
11
ms
12
ms
38
ms
145
ms
19
Input Resistance
FAN RPMTODIGITAL CONVERTER
For VCCP channel
70
120
kW
Accuracy
FullScale Count
Nominal Input RPM
0°C TA 70°C
40°C TA +120°C
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
109
329
5000
10,000
±6
±10
65,535
%
RPM
OPENDRAIN DIGITAL OUTPUTS (PWM1 TO PWM3, XTO)
Current Sink, IOL
Output Low Voltage, VOL
IOUT = 8.0 mA
High Level Output Current, IOH
VOUT = VCC
OPENDRAIN SERIAL DATA BUS OUTPUT (SDA)
8.0
mA
0.4
V
0.1
20
mA
Output Low Voltage, VOL
High Level Output Current, IOH
SMBus DIGITAL INPUTS (SCL, SDA)
IOUT = 4.0 mA
VOUT = VCC
0.4
V
0.1
1.0
mA
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
2.0
V
0.4
V
500
mV
Input High Voltage, VIH
2.0
V
Maximum input voltage
3.6
Input Low Voltage, VIL
Minimum input voltage
0.8
V
0.3
Hysteresis
0.5
V pp
1. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25°C and represent the most likely
parametric norm. Logic inputs accept input high voltages of up to VMAX, even when the device is operating down to VMIN. Timing
specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
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