ADT7481ARMZ-1RL(2014) 查看數據表（PDF） - ON Semiconductor
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ADT7481ARMZ-1RL Datasheet PDF : 20 Pages
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ADT7481
Table 3. PIN ASSIGNMENT
Pin No.
1
2
3
4
Mnemonic
VDD
D1+
D1−
THERM
5
GND
6
D2−
7
D2+
8
ALERT/THERM2
9
SDATA
10
SCLK
Description
Positive Supply, 3.0 V to 3.6 V.
Positive Connection to the Remote 1 Temperature Sensor.
Negative Connection to the Remote 1 Temperature Sensor.
Open-Drain Output. Requires pullup resistor. Signals overtemperature events, could be used to turn a
fan on/off, or throttle a CPU clock.
Supply Ground Connection.
Negative Connection to the Remote 2 Temperature Sensor.
Positive Connection to the Remote 2 Temperature Sensor.
Open-Drain Logic Output. Used as interrupt or SMBALERT. This may also be configured as a second
THERM output. Requires pullup resistor.
Logic Input/Output, SMBus Serial Data. Open-Drain Output. Requires pullup resistor.
Logic Input, SMBus Serial Clock. Requires pullup resistor.
Table 4. TIMING SPECIFICATIONS (Note 1)
Parameter
Limit at TMIN and TMAX
fSCLK
400
tLOW
1.3
tHIGH
0.6
tR
300
tF
300
tSU; STA
600
tHD; STA (Note 2)
600
tSU; DAT (Note 3)
100
tHD; DAT
300
tSU; STO (Note 4)
600
tBUF
1.3
1. Guaranteed by design, not production tested.
2. Time from 10% of SDATA to 90% of SCLK.
3. Time for 10% or 90% of SDATA to 10% of SCLK.
4. Time for 90% of SCLK to 10% of SDATA.
Unit
kHz max
ms min
ms min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ms min
Description
Clock low period, between 10% points.
Clock high period, between 90% points.
Clock/data rise time.
Clock/data fall time.
Start condition setup time.
Start condition hold time.
Data setup time.
Data hold time.
Stop condition setup time.
Bus free time between stop and start conditions.
SCLK
SDATA
tBUF
STOP START
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
START
Figure 2. Serial Bus Timing
tSU; STO
STOP
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