ADT7484A 查看數據表（PDF） - ON Semiconductor

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ADT7484A

Digital Temperature Sensor with SST Interface

ON Semiconductor 

ADT7484A/ADT7486A

ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, = VCC = VMIN to VMAX, unless otherwise noted)

Parameter

Conditions

Min

Typ

Temperature-to-Digital Converter

Conversion Time (Local Temperature)

Averaging enabled

12

(Note 1)

Conversion Time (Remote Temperature)

(Note 1)

Averaging enabled

Total Monitoring Cycle Time (Note 1)

Averaging enabled

Digital Inputs (ADD0, ADD1)

Input High Voltage, VIH

Input Low Voltage, VIL

Input High Current, IIH

Input Low Current, IIL

Pin Capacitance

VIN = VCC

VIN = 0

2.3

−1.0

5.0

Digital I/O (SST Pin)

Input High Voltage, VIH

Input Low Voltage, VIL

Hysteresis (Note 1)

Between input switching levels

1.1

150

Output High Voltage, VOH

ISOURCE = 6 mA (maximum)

1.1

High Impedance State Leakage, ILEAK

Device powered on SST bus;

VSST = 1.1 V, VCC = 3.3 V

High Impedance State Leakage, ILEAK

Device unpowered on SST bus;

VSST = 1.1 V, VCC = 0 V

Signal Noise Immunity, VNOISE

Noise glitches from

300

10 MHz to 100 MHz; width up to 50 ns

SST Timing

Bitwise Period, tBIT

High Level Time for Logic 1, tH1

(Note 2)

tBIT defined in speed negotiation

0.495

0.6 x tBIT

0.75 x tBIT

High Level Time for Logic 0, tH0

(Note 2)

0.2 x tBIT 0.25 x tBIT

Time to Assert SST High for Logic 1,

tSU, HIGH

Hold Time, tHOLD (Note 3)

Stop Time, tSTOP

See SST Specification Rev 1.0

Device responding to a constant low

level driven by originator

1.25 x tBIT

2 x tBIT

Time to Respond After a Reset, tRESET

Response Time to Speed Negotiation

Time after powerup when device can

500

After Powerup

participate in speed negotiation

1. Guaranteed by design, not production tested.

2. Minimum and maximum bit times are relative to tBIT defined in the timing negotiation pulse.

3. Devices compatible with hold time specification as driven by SST originator.

Max

12

38

50

0.8

1.0

0.4

1.9

±1.0

±10

500

0.8 x tBIT

0.4 x tBIT

0.2 x tBIT

0.5 x tBIT−M

2 x tBIT

0.4

Unit

ms

ms

ms

V

V

mA

mA

pF

V

V

mV

V

mA

mA

mV

p-p

ms

ms

ms

ms

ms

ms

ms

ms

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