ADT7490ARQZ 查看數據表（PDF） - ON Semiconductor
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ADT7490ARQZ Datasheet PDF : 75 Pages
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ADT7490
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
Digital I/O (PECI Pin) (Note 2)
VTT, Supply Voltage
Input High Voltage , VIH
0.95
0.55 x VTT
(Note 3)
1.26
V
V
Input Low Voltage, VIL
0.5 x VTT
V
(Note 3)
Hysteresis (Note 2)
Hysteresis between input switching
0.1 x VTT
mV
levels
(Note 3)
High Level Output Source Current,
ISOURCE
VOH = 0.75 x VTT
Low Level Output Sink Current, ISINK
VOL = 0.25 x VTT
0.5
Signal Noise Immunity, VNOISE
Noise glitches from 10 MHz to
300
100 MHz, width up to 50 ns
6.0
mA
1.0
mA
mV
p−p
Digital Input Logic Levels (TACH1 to TACH3)
Input High Voltage, VIH
Maximum input voltage
2.0
V
5.5
Input Low Voltage, VIL
Minimum input voltage
0.8
V
−0.3
Hysteresis
Digital Input Logic Levels (THERM)
0.5
V p−p
Input High Voltage, VIH
Input Low Voltage, VIL
Digital Input Current
0.75 x VCCP
V
0.4
V
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
Serial Bus Timing (Note 2)
VIN = VCC
VIN = 0
(See Figure 2)
±1
mA
±1
mA
5.0
pF
Clock Frequency, fSCLK
10
400
kHz
Glitch Immunity, tSW
50
ns
Bus Free Time, tBUF
4.7
ms
SCL Low Time, tLOW
4.7
ms
SCL High Time, tHIGH
4.0
50
ms
SCL, SDA Rise Time, tr
1000
ns
SCL, SDA Fall Time, tf
300
ms
Data Setup Time, tSU;DAT
250
ns
Detect Clock Low Timeout, tTIMEOUT
Can be optionally disabled
15
35
ms
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a parametric norm.
Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic
levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge.
2. Guaranteed by design, not production tested.
3. VTT is the voltage input on Pin 8. The VTT voltage is determined by the processor installed on the system.
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