ADV7122 查看數據表（PDF） - Analog Devices

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ADV7122

CMOS 80 MHz, Triple 10-Bit Video DACs

Analog Devices 

ADV7121/ADV7122

PIN FUNCTION DESCRIPTION

Pin

Mnemonic

Function

BLANK*

Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,

IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While

BLANK is a logical zero, the R0–R9, G0–G9 and R0–R9 pixel inputs are ignored.

SYNC*

Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE

current source. This is internally connected to the IOG analog output. SYNC does not override any other

control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the

rising edge of CLOCK.

If sync information is not required on the green channel, the SYNC input should be tied to logical zero.

CLOCK

Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and

BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be

driven by a dedicated TTL buffer.

R0–R9,

G0–G9,

B0–B9

Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.

R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the

regular PCB power or ground plane.

IOR, IOG, IOB Red, green, and blue current outputs. These high impedance current sources are capable of directly driving a

doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not

they are all being used.

FS ADJUST Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of the

full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.

The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG)

is given by:

RSET (Ω)

= 12,082 × VREF (V)/IOG (mA)

The relationship between RSET and the full-scale output current on IOR, IOG and IOB is given by:

IOG* (mA)

IOR, IOB (mA)

= 12,082 × VREF (V)/RSET (Ω) (SYNC being asserted)

= 8,628 × VREF (V)/RSET (Ω)

The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used, i.e., SYNC

tied permanently low. For the ADV7121, all three analog output currents are as described by:

COMP

VREF

VAA

GND

IOR, IOG, IOB (mA)

= 7,969 × VREF (V)/RSET (Ω)

Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor

must be connected between COMP and VAA.

Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. The use of an

external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be

connected between VREF and VAA.

Analog power supply (5 V ± 5%). All VAA pins on the ADV7121/ADV7122 must be connected.

Ground. All GND pins must be connected.

*SYNC and BLANK functions are not provided on the ADV7121.

–6–

REV. B

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