ADV7129 查看數據表（PDF） - Analog Devices
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ADV7129 Datasheet PDF : 20 Pages
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ADV7129
TIMING SPECIFICATIONS (VAA2 = +5 V, VREF = +1.235 V, RRSET, RGSET, RBSET = 280 ⍀, RL = 25 ⍀ for IOG, IOR, IOB, CL = 10 pF.
All specifications TMIN to TMAX3 unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Units
CLOCK CONTROL & PIXEL PORT4
LOADIN Clocking Rate, fLCLK
LOADIN Cycle Time, t1
LOADIN Low Time, t2
LOADIN High Time, t3
LOADIN to LOADOUT Delay, t4
Pixel Setup Time, t5
Pixel Hold Time, t6
MPU PORT
R/W, C0, C1 Setup Time, t7
R/W, C0, C1 Hold Time, t8
CE Low Time, t9
CE High Time, t10
CE Asserted to Data-Bus Driven, t11
CE Asserted to Data-Bus Valid, t12
CE Negated to Data-Bus Invalid, t13
CE Negated to Data-Bus Three Stated, t14
Write Data (D7–D0) Setup Time, t15
Write Data (D7–D0) Hold Time, t16
ANALOG OUTPUTS5
Analog Output Delay, t17
Analog Output Rise/Fall Time, t18
Analog Output Transition Time, t19
RGB Analog Output Skew, tSK
Pipeline Delay, tPD
PLL PERFORMANCE6
Jitter (1σ)
@ 360 MHz
(LOADIN = 45 MHz)
10
45
16.67
6.67
6.67
5
1
0
4
2
10
2.5
10
0.5
25
25
2
5
20
1
15
10
10
5
0.8
25
1.5
19
55
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCLKs
ps rms
NOTES
1TTL inputs values are 0 V to 3 V with input rise/fall times ≥3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. Analog output load ≤10 pF. Databus (D7–D0) loaded as shown in Figure 1. Digital output load for SENSE ≤30 pF.
2± 5% for all versions.
3Temperature range (TMIN to TMAX), 0°C to +70°C.
4Pixel Port consists of the following inputs: Pixel Inputs: RED [A-H], BLUE [A-H], GREEN [A-H].
5Output Delay is measured from the 50% rising edge of LOADIN to the 50% point of full-scale transition on the A pixel. t17 includes the analog delay due to DACs
and internal gate transitions plus the pipeline stages delay. The output delay for pixels B-H will be the output delay to the A pixel (t 17) plus the appropriate number
of clock cycles. Output rise/fall time is measured between the 10% and 90% points of full-scale transition. Settling time is measured from the 50% point of full-scale
transition to the output remaining within 1%. (Settling Time does not include clock and data feedthrough.)
6Jitter is measured by triggering on the output clock, delayed by 15 µs and then measuring the time period from the trigger edge to the next edge of the output clock
after the delay. This measurement is repeated multiple times and the rms value is determined.
Specifications subject to change without notice.
ISINK
TO OUTPUT PIN
100pF
+2.1V
ISOURCE
Figure 1. LOADIN vs. Pixel Input Data
REV. 0
–3–
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