AHA4013B-050PJC 查看數據表（PDF） - Unspecified
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AHA4013B-050PJC Datasheet PDF : 28 Pages
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Advanced Hardware Architectures, Inc.
2.7 ENCODE, DECODE OR PASS-THROUGH OPERATIONS
The device performs three functions: encoding,
decoding and pass-through. As an encoder the device
outputs the message block followed by “corrected”
check bytes. As a decoder, the device outputs the
corrected message bytes or correction vectors with or
without check bytes following the message. In pass-
through operation, the device passes the input data as
it is received. In all three operations, the input block
flows through the Input Buffer into the ECC module
and out of the Output Buffer. Latencies for all three
operations are the same.
The device is initialized for the three operations
as shown in the table below.
Table 1: Initialization Register Settings for Encode, Decode and Pass-Through Operations
INITIALIZATION
REGISTER
BIT(S)
ENCODE
DECODE PASS-THROUGH
ERASURE MULTIPLIER
[7:0]
Appendix A value Appendix A value Appendix A value
ERROR THRESHOLD
[7:0]
Set to R
R or less
R
CHECK BYTES
[7:0]
Set to R
R
R
MESSAGE BYTES
BLOCK LENGTH
Set to the Number
[7:0]
of Message Bytes K
K
in block, K
Set to the total of
[7:0]
Message and
N
N
Check bytes, N
0 (RESV) 0
0
0
1 (NOPAR) 0
System specific 0
2 (CRCTS) 1
System specific 1
CONTROL BYTE
3 (FOR) System specific
4 (RAW) 0
5 (ERC) 0
[7:6] Reserved 0
System specific
0
System specific
0
System specific
1
0
0
As an encoder, the device is used with the
Erasures feature enabled in the following sequence.
(Asserting the ERASE signal high enables the
Erasure feature.)
1) After initialization, the device receives the
message data followed by “dummy” check
bytes. “Dummy” check bytes are clocked
into the device with the ERASE signal
asserted. The number of “dummy” check
bytes must equal R.
2) The ECC core processes the block by
“correcting” the check bytes and feeding
the codeword into the Output Buffer in
reverse order.
3) The block is then made available on the
output bus, DO. The state of the output
RDYON determines the availability of
data. ERR signal is asserted while the
“corrected check bytes” are output on the
output bus, DO. CRTN is asserted low
during the last byte out of the chip
indicating that the previous block did not
exceed the error threshold.
As a decoder, the device works similar to the
encode operation in the following sequence.
1) Following initialization, the system clocks
the message data and the check bytes into
the Input Buffer. ERASE signal may be
asserted as desired by the system. State of
the output signal, RDYIN determines the
chip’s ability to accept data input on the DI
bus.
2) The ECC Core processes the block by
performing necessary corrections, and
feeds the codeword into the Output Buffer
in reverse order.
3) The data is available on the output port. The
state of the output signal, RDYON
determines the availability of valid data. An
output byte which has been corrected is
indicated by the device asserting ERR.
CRTN may be high or low depending upon
the THRESHOLD Register and ERC bit
programmed and the errors encountered.
PS4013B-0600
Page 7 of 24
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