AHA4013B-050PJC 查看數據表（PDF） - Unspecified
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AHA4013B-050PJC Datasheet PDF : 28 Pages
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Advanced Hardware Architectures, Inc.
1.2.1 DEFINITION OF CORRECTION TERMS
TERM
NAME
(other references)
K
Message Length (user
data or message bytes)
R
Check Symbols
(parity or redundancy)
N
Codeword Length
(block length)
t Error Corrections
P Error Threshold
e Number of Errors
E Number of Erasures
G Burden of Correction
DEFINITION
RANGE
(number of bytes)
Number of user data symbols in one message block.
Size of a symbol in AHA4013B is 8-bits. Message 1 through 253
length is K = N − R. The first message byte is
(1, 2, 3, 4... 253)
referred to as XK−1; the last message byte is X0.
Symbols appended to the user data to detect and
correct errors. The number of check symbols
2 through 20 in
required in a system is R ≥ E + 2e.* The first check increments of 1
symbol is referred to as YR−1; the last check symbol (2, 3, 4... 20)
is Y0.
Sum of message and check symbols. N = K + R.
3 through 255
(3, 4, 5, 6... 255)
Maximum number of error corrections performed 1 through 10
by the device. The value is t = Integer N------–2-----K--- .
(1, 2, 3... 10)
The threshold limit to determine uncorrectability of
a Codeword and the number of check bytes
2 through 20
allocated for correction-only purposes (not for (2, 3, 4... 20)
detection).
An error is defined as an erroneous byte whose
correct value and position within the message block 0 through N
are both unknown.
An erasure is defined as an error whose position is
known within the message block.**
0 through N
A measure of the burden of correction being placed
on the capabilities of the device for that message 0 through R
block. The value G = 2e + E.
* For every 2 check bytes, the AHA4013B can correct either 2 erasures or 1 error.
** An erasure is detected by a parity detector or a signal dropout detector. The presence of an erasure is indicated
by asserting the ERASE signal when the erased byte is clocked into the AHA4013B.
2.0 FUNCTIONAL DESCRIPTION
This section describes an architectural
overview of the chip and its many functions,
features and operations. The block diagram for the
chip shows the Reed-Solomon ECC module, the
Input and Output Buffers, and their associated
control. All input and output data are clocked on the
rising edge of CLK.
2.1 FUNCTIONAL OVERVIEW
The AHA4013B Reed-Solomon codec (coder/
decoder) is a member of the AHA PerFEC™ family
of high speed forward error correction (FEC) devices.
This single chip, three-layer metal, CMOS device can
operate in encode, decode or pass-through modes.
The ECC core implements a full error
correcting Reed-Solomon decoder. This code is
capable of correcting up to 10 (t=10) byte-errors or
20 (t=10) erasures in a RS block.
The ECC core has three phases of operation:
Data In, Calculation and Data Out. Data to be
processed is first input into a single ported Input
Buffer using a control signal DSIN. ECC core
arbitrates for the input data out of the Input Buffer.
ECC core has access to the Input Buffer on clock
edges where DSIN is not asserted.
Each block is processed within the ECC core
and calculations are made. The entire block is
processed through the ECC core, and transferred
into the Output Buffer. The device asserts RDYON
signal and holds active until the Output Buffer is
completely emptied.
The ECC core loads the Output Buffer in
reverse order for either operation. Data may be
strobed out of the device in forward or reverse order.
If forward order is desired, output data cannot be
strobed out of the device until the entire block has
been loaded into the Output Buffer.
Page 2 of 24
PS4013B-0600
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