AIC1650CS 查看數據表（PDF） - Analog Intergrations
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AIC1650CS Datasheet PDF : 6 Pages
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PIN DESCRIPTIONS
PIN 1: VIN - 4V to 20V input supply voltage.
PIN 2: VREF - 1.22V reference output. Bypass
with a 0.047µF capacitor to GND.
Sourcing capability is guaran-
teed to be greater than 250µA.
PIN 3:
SHDN- Logic input to shutdown the chip.
>1.5V = normal operation,
GND = shutdown
In shutdown mode DLOW and
DHI pins are at high level.
PIN 4: FB
- Feedback signal input to sense
ground. Connecting a resistor
R1 to VOUT and a resistor R2 to
VREF pin yields the output volt-
age:
VOUT = -(R1/R2 ) x VREF
PIN 5: GND - Power ground.
AIC1650
PIN 6: DLOW - Driver sinking output. Connected
to DHI when using an external
P-channel MOSFET. When us-
ing an external PNP bipolar
transistor, connect a resistor RB
from this pin to DHI. RB value
depends on VIN, inductor and
PNP bipolar transistor. By ad-
justing the RB value, efficiency
can be optimized.
PIN 7: DHI
- Driver sourcing output. Connect
to gate of the external P-channel
MOSFET or base of the PNP bi-
polar transistor.
PIN 8: CL
- Current-limit input. This pin
clamps the switch peak current
to prevent over-current damage
to the external switch.
APPLICATION INFORMATIONS
Max. Output Power vs VIN
1.8
1.6 Typical Application Circuit
1.4
1.2
1
0.8
0.6
100µH
120µH
150µH
180µH
220µH
270µH
0.4
330µH
300µH
0.2
Inductor Value
0
4
6
8
10
12
14
16
18
20
VIN (V)
The typical application circuit generates an adjustable
negative voltage for contrast bias of LCD displays.
Efficiency and output power can be optimized by us-
ing appropriate inductor and switch. The following
formulas provide a guideline for determining the op-
timal component values:
L
=
(11.1 − 0.15 × VIN) ×
V IN
IOUT × V OUT
PNP : V CEO > VIN + V OUT
I C, MAX
≥ 200 ×
IOUT
VIN
V CE
< 0. 4V at
I
C
=
200
×
IOUT
V IN
and β = 10
RB ≅ 3 x L x (VIN - 0.8)
where, units: VIN & VOUT in V, IOUT in A, L in µH,
RB in Ω
4
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