AK2510 查看數據表（PDF） - Asahi Kasei Microdevices

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产品描述 (功能)

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AK2510

Voice Switch LSI for Hands-Free Phone

Asahi Kasei Microdevices 

ASAHI KASEI

[AK2510]

2 Timing and format of the PCM interface

2-1 u/A-Law PCM data Mode

8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.

Although there are 32 time slots at maximum in 8kHz frame(when BCK=2.048MHz), PCM data for AK2510

occupies the first time slot as is indicated in figures below.

2-1-a Signals

- Frame Sync signal (FS)

8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interfa ce.

- Bit Clock (BCLK)

BCLK defines the PCM data rate. BCLK can be varied 512kHz or 2.048MHz.

- PCM data output (TOUT, ROUT)

TOUT and ROUT are output signal of 64Kbps PCM u/A-law data. The data is synchronized to the BCLK which

determines the data rate. In the period in which the PCM data is not occupied, the TOUT, ROUT pins turns to

Hi-impedance. In the long frame mode, the LSB bit turns to Hi -impedance at the faster edge of either FS falling

edge or 9th rising edge of BCLK.

- PCM data input (TIN, RIN)

TIN and RIN are input signal of 64Kbps PCM u/A-law data. The data is clocked by the falling edge of BCLK and

fed into the PCM interface block.

2-1-b LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic selection

AK2510 monitors the duration of the “H” level of FS and automatically selects LF or SF interface format.

Period of FS=”H”

Interface format

More than 2 clocks of BCLK

LF

1 clock of BCLK

SF

2-1-c Frame format of the interface

Long Frame format

M o re th a n 2 C lo c ks

FS

BCLK

1 25 us(8K H z)

DX

7

6

5

4

3

2

10

DR

D o n ’t

c a re

7

6

5

4

3

2

10

D o n ’t c a re

Short Frame format

FS

BCLK

DX

DR

D on’t

care

125us(8KHz)

7 6 5 4 3 2 10

76543210

D on’t care

AKM

-9-

AK2510-E-00

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