AK7742 查看數據表（PDF） - Asahi Kasei Microdevices

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AK7742

24bit 2ch ADC + 24bit 4ch DAC with Audio DSP

Asahi Kasei Microdevices 

[AK7742]

SWITCHING CHARACTERISTICS

■ System Clock

(Ta=-20ºC~70ºC; AVDD=DVDD=3.0~3.6V)

Parameter

Symbol

min

XTI

a)with a crystal oscillator

Frequency(256fs)

fs=44.1KHz fXTI

-

CKM[2:0]= 000

fs=48KHz

CKM[2:0]= 001

fXTI

-

b)with an external clock

Duty cycle

Duty

40

Frequency(256fs)

fs=44.1KHz fXTI

11.0

CKM[2:0]= 000, 010

fs=48KHz

Frequency (384fs)

fs=44.1KHz fXTI

16.5

CKM[2:0]= 001

fs=48KHz

LRCK frequency (Note 23)

Fs

7.35

typ

11.2896

12.288

16.9344

18.432

50

11.2896

12.288

16.9344

18.432

48

max

Unit

-

MHz

-

MHz

60

%

12.4

MHz

18.6

MHz

96

kHz

BICK frequency

a) CKM[2:0]= 001, 010

32

64

fs

High level width

tBCLKH

64

ns

Low level width

tBCLKL

64

ns

Frequency

fBCLK

0.46

3.072

6.144

MHz

b) CKM[2:0]= 011 (Note 25)

64

fs

Duty cycle

Duty

40

50

60

%

Frequency

fBCLK

2.75

3.072

3.1

MHz

c) CKM[2:0]= 100 (Note 26)

32

fs

Duty cycle

Duty

40

50

60

%

Frequency

fBCLK

230

256

258

kHz

d) CKM[2:0]= 101 (Note 27)

64

fs

Duty cycle

Duty

40

50

60

%

Frequency

fBCLK

460

512

516

kHz

Note 23. LRCK frequency and sampling rate (fs) should be the same.

Note 24. The BICK must be divided 32, 48 or 64 clocks correctly. (BICK can be selected from 32fs, 48fs or 64fs)

Note 25. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.

Note 26. When BICK is resource of internal MCLK. The BICK must be divided 32 clocks correctly. 32fs fixed.

Note 27. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.

Rev.0.5b_PB

- 11 -

2008/08

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