M28256 查看數據表（PDF） - STMicroelectronics
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M28256 Datasheet PDF : 20 Pages
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M28256
nal timing control, until the write operation is com-
plete. The commencement of this period can be
detected by reading the Page Load Timer Status
on DQ5. The end of the cycle can be detected by
reading the status of the Data Polling and the Tog-
gle Bit functions on DQ7 and DQ6.
Page Write
The Page Write mode allows up to 64 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write op-
erations, no two of which are separated by more
than the tWLQ5H value (as specified in Table 9A
and Table 9B).
The page write can be initiated during any byte
write operation. Following the first byte write in-
struction the host may send another address and
data with a minimum data transfer rate of:
1/tWLQ5H.
The internal write cycle can start at any instant af-
ter tWLQ5H. Once initiated, the write operation is in-
ternally timed, and continues, uninterrupted, until
completion.
All bytes must be located on the same page ad-
dress (A14-A6 must be the same for all bytes).
Otherwise, the Page Write operation is not execut-
ed.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled write-pro-
tection mechanism that allows the user to inhibit all
write operations to the device. This can be useful
for protecting the memory from inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).
By default, the device is shipped in the “unprotect-
ed” state: the memory contents can be freely
changed by the user. Once the Software Data Pro-
tection Mode is enabled, all write commands are
ignored, and have no effect on the memory con-
tents.
The device remains in this mode until a valid Soft-
ware Data Protection disable sequence is re-
ceived. The device reverts to its “unprotected”
state.
The status of the Software Data Protection (en-
abled or disabled) is represented by a non-volatile
latch, and is remembered across periods of the
power being off.
The Software Data Protection Enable command
consists of the writing of three specific data bytes
Figure 4. Software Data Protection Enable Algorithm and Memory Write
SDP
Set
SDP
not Set
Write AAh in
Address 5555h
Write AAh in
Address 5555h
Page Write
Timing
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
Page Write
Timing
Write 55h in
Address 2AAAh
Write A0h in
Address 5555h
SDP is set
Write Data to
be Written in
any Address
SDP ENABLE ALGORITHM
Write
in Memory
Write Data
+
SDP Set
after tWC
AI01698C
Note: 1. The most significant address bits (A14 to A6) differ during these specific Page Write operations.
Write
is enabled
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