M28256 查看數據表（PDF） - STMicroelectronics
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M28256 Datasheet PDF : 20 Pages
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M28256
Figure 5. Software Data Protection Disable Algorithm
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Page Write
Timing
Write 80h in
Address 5555h
Write AAh in
Address 5555h
Write 55h in
Address 2AAAh
Write 20h in
Address 5555h
Unprotected State
after
tWC (Write Cycle time)
AI01699C
to three specific memory locations (each location
being on a different page), as shown in Figure 4.
Similarly to disable the Software Data Protection,
the user has to write specific data bytes into six dif-
ferent locations, as shown in Figure 5. This com-
plex series of operations protects against the
chance of inadvertent enabling or disabling of the
Software Data Protection mechanism.
When SDP is enabled, the memory array can still
have data written to it, but the sequence is more
complex (and hence better protected from inad-
vertent use). The sequence is as shown in Figure
4. This consists of an unlock key, to enable the
write action, at the end of which the SDP continues
to be enabled. This allows the SDP to be enabled,
and data to be written, within a single Write cycle
(tWC).
Status Bits
The devices provide three status bits (DQ7, DQ6
and DQ5), and one output pin (RB), for use during
write operations. These allow the application to
use the write time latency of the device for getting
on with other work. These signals are available on
the I/O port bits DQ7, DQ6 and DQ5 (but only dur-
ing programming cycle, once a byte or more has
been latched into the memory) or continuously on
the RB output pin.
Data Polling bit (DQ7). The internally timed write
cycle starts after tWLQ5H (defined in Table 9A and
Table 9B) has elapsed since the previous byte
was latched in to the memory. The value of the
DQ7 bit of this last byte, is used as a signal
throughout this write operation: it is inverted while
the internal write operation is underway, and is in-
verted back to its original value once the operation
is complete.
Toggle bit (DQ6). The device offers another way
for determining when the internal write cycle is
completed. During the internal Erase/Write cycle,
DQ6 toggles from ’0’ to ’1’ and ’1’ to ’0’ (the first
read value being ’0’) on subsequent attempts to
read any byte of the memory. When the internal
Figure 6. Status Bit Assignment
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
DP TB PLTS X
X
X
X
X
DP
TB
PLTS
X
= Data Polling
= Toggle Bit
= Page Load Timer Status
= Don’t Care
AI02855
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