AM188ES-33VCW 查看數據表（PDF） - InnovASIC, Inc

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AM188ES-33VCW

8-Bit/16-Bit Microcontrollers

InnovASIC, Inc 

IA186ES/IA188ES

8-Bit/16-Bit Microcontrollers

Data Sheet

November 15, 2011

LIST OF FIGURES

Figure 1. IA186ES TQFP Package Diagram ................................................................................17

Figure 2. IA188ES TQFP Package Diagram ................................................................................20

Figure 3. TQFP Package Dimensions ...........................................................................................23

Figure 4. IA186ES PQFP Package Diagram ................................................................................24

Figure 5. IA188ES PQFP Package Diagram ................................................................................27

Figure 6. PQFP Package Dimensions ...........................................................................................30

Figure 7. Functional Block Diagram ............................................................................................48

Figure 8. Crystal Configuration ....................................................................................................49

Figure 9. Organization of Clock ...................................................................................................49

Figure 10. DMA Unit....................................................................................................................58

Figure 11. Typical Waveform at the int2/int0_n/pwd pin ............................................................59

Figure 12. Read Cycle.................................................................................................................113

Figure 13. Multiple Read Cycles ................................................................................................114

Figure 14. Write Cycle................................................................................................................116

Figure 15. Multiple Write Cycles ...............................................................................................117

Figure 16. PSRAM Read Cycle ..................................................................................................119

Figure 17. PSRAM Write Cycle .................................................................................................121

Figure 18. PSRAM Refresh Cycle..............................................................................................123

Figure 19. Interrupt Acknowledge Cycle....................................................................................124

Figure 20. Software Halt Cycle ..................................................................................................126

Figure 21. Clock—Active Mode.................................................................................................128

Figure 22. Clock—Power-Save Mode ........................................................................................128

Figure 23. srdy—Synchronous Ready ........................................................................................129

Figure 24. ardy—Asynchronous Ready......................................................................................130

Figure 25. Peripherals .................................................................................................................130

Figure 26. Reset 1 .......................................................................................................................131

Figure 27. Reset 2 .......................................................................................................................131

Figure 28. Bus Hold Entering .....................................................................................................132

Figure 29. Bus Hold Leaving......................................................................................................132

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