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HYB314171BJ 查看數據表(PDF) - Siemens AG

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HYB314171BJ Datasheet PDF : 24 Pages
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3.3V 256 K x 16-Bit Dynamic RAM
3.3V Low Power 256 K x 16-Bit
Dynamic RAM with Self Refresh
HYB 314171BJ-50/-60/-70
HYB 314171BJL-50/-60/-70
Preliminary Information
262 144 words by 16-bit organization
0 to 70 °C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
70 ns (-70 version)
CAS access time:
15ns (-50,-60 version)
20 ns (-70 version)
Cycle time:
95 ns (-50 version)
110 ns (-60 version)
130 ns (-70 version)
Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
45 ns (-70 version)
Single + 3.3 V (± 0.3 V) supply with a built-
in VBB generator
Low Power dissipation
max. 450 mW active (-50 version)
max. 378 mW active (-60 version)
max. 306 mW active (-70 version)
Standby power dissipation
7.2 mW standby (TTL)
3.6 mW max. standby (CMOS)
0.72 mW max. standby (CMOS) for
Low Power Version
Output unlatched at cycle end allows two-
dimensional chip selection
Read, write, read-modify write, CAS-
before-RAS refresh, RAS-only refresh,
hidden-refresh and fast page mode
capability
2 CAS / 1 WE control
Self Refresh (L-Version)
All inputs and outputs TTL-compatible
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms
Low Power Version only
Plastic Packages:
P-SOJ-40-1 400mil width
The HYB 314171BJ/BJL is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The
HYB 314171BJ/BJL utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 314171BJ/BJL to be packed in a standard plastic 400mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include Self Refresh (L-
Version), single + 3.3 V (± 0.3 V) power supply, direct interfacing with high performance logic
device families.
Semiconductor Group
1
7.96

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