AM28F020 查看數據表（PDF） - Advanced Micro Devices
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AM28F020 Datasheet PDF : 35 Pages
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addresses and data needed for the programming and
erase operations. For system design simplification, the
Am28F020 is designed to support either WE# or CE#
controlled writes. During a system write cycle,
addresses are latched on the falling edge of WE# or
CE#, whichever occurs last. Data is latched on the rising
edge of WE# or CE#, whichever occurs first. To simplify
discussion, the WE# pin is used as the write cycle
control pin throughout the rest of this data sheet. All
setup and hold times are with respect to the WE# signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F020 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM
programming mechanism of hot electron injection.
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options (VCC = 5.0 V ± 10%)
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
Am28F020
-70
-90
-120
-150
-200
70
90
120
150
200
70
90
120
150
200
35
35
50
55
55
BLOCK DIAGRAM
VCC
VSS
VPP
WE#
CE#
OE#
State
Control
Command
Register
Erase
Voltage
Switch
To Array
Program
Voltage
Switch
Chip Enable
Output Enable
Logic
Program/Erase
Pulse Timer
Y-Decoder
DQ0–DQ7
Input/Output
Buffers
Data Latch
Y-Gating
Low VCC
Detector
A0–A17
X-Decoder
2,097,152
Bit
Cell Matrix
14727F-1
2
Am28F020
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