NT512D64S8HA0G-7K 查看數據表（PDF） - Nanya Technology

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NT512D64S8HA0G-7K

184pin Two Bank Unbuffered DDR SDRAM MODULE

Nanya Technology 

NT512D64S8HAAG

512MB : 64M x 64

PC2100 / PC1600 Unbuffered DIMM

Operating, Standby, and Refresh Currents

(TA = 0 °C ~ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;

I DD0

tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating Current : one bank; active / read / precharge; Burst = 2;

I DD1

tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;

address and control inputs changing once per clock cycle

I DD2P

Precharge Power-Down Standby Current :

all banks idle; power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

I DD2N

Idle Standby Current : CS ≥ VIH (MIN) ; all banks idle; CKE ≥ VIH(MIN) ;

tCK = tCK (MIN) ; address and control inputs changing once per clock cycle

I DD3P

Active Power-Down Standby Current : one bank active;

power-down mode; CKE ≤ VIL (MAX) ; tCK = tCK (MIN)

Active Standby Current : one bank; active / precharge; CS ≥ VIH (MIN) ;

I DD3N

CKE ≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS

inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating Current : one bank; Burst = 2; reads; continuous burst;

I DD4R

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5;

tCK = tCK (MIN) ; IOUT = 0mA

Operating Current : one bank; Burst = 2; writes; continuous burst;

I DD4W

address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5;

tCK = tCK (MIN)

I DD5 Auto-Refresh Current :

t RC = t RFC (MIN)

t RC = 7.8 µs

I DD6

I DD7

Self-Refresh Current : CKE ≤ 0.2V

Operating Current: four bank; four bank interleaving with BL = 4, address

and control inputs randomly changing; 50% of data changing at every

transfer; tRC = tRC (min); IOUT = 0mA.

1. I DD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Enables on-chip refresh and address counters.

4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

PC1600

1024

1760

400

480

400

800

1418

1288

2256

264

48

4000

PC2100

1160

Unit Notes

mA

1,2

1920

400

560

400

mA

1,2

mA

1,2

mA

1,2

mA

1,2

960

mA

1,2

1800

mA

1,2

1680

2400

264

48

4800

mA

1,2

mA

1,2

mA

1,2,4

mA

1,2,3

mA

1

REV 1.0 06 / 2002

10

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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