V436632Y24V 查看數據表（PDF） - Mosel Vitelic Corporation
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V436632Y24V Datasheet PDF : 12 Pages
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MOSEL VITELIC
SPD-Table for modules: (Continued)
Byte
Number
29
30
31
64
33
34
35
62-61
62
63
64
65-71
72
73-90
91-92
93
94
95-98
99-125
126
127
128+
Function Described
SPD Entry Value
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (Per Bank)
15 ns/20 ns
42 ns/45 ns
128 Mbyte
SDRAM Input Setup Time
1.5 ns/2.0 ns
SDRAM Input Hold Time
0.8 ns/ 1.0 ns
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
Superset Information (May be used in Future)
SPD Revision
Revision 2 / 1.2
Checksum for Bytes 0 - 62
Manufacturer’s JEDEC ID Code
Mosel Vitelic
Manufacturer’s JEDEC ID Code (cont.)
Manufacturing Location
1 = US, 2 = Taiwan
Module Part Number (ASCII)
V436632Y24V
PCB Identification Code
Current PCB Revision
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
Reserved
Intel Specification for Frequency
Supported Frequency
Unused Storage Location
-75PC
0F
2A
20
15
08
15
08
00
02
E5
40
00
00
64
00
V436632Y24V
Hex Value
-75
14
2D
20
15
08
15
08
00
02
2A
40
00
-10PC
14
2D
20
20
10
20
10
00
12
98
40
00
00
00
64
64
00
00
V436632Y24V Rev. 1.2 March 2002
5
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