HYB39S256160T-8B 查看數據表（PDF） - Infineon Technologies
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HYB39S256160T-8B Datasheet PDF : 46 Pages
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HYB39S256400/800/160T
256MBit Synchronous DRAM
Operating Currents (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V
(Recommended Operating Conditions unless otherwise noted)
Parameter & Test Condition
OPERATING CURRENT
trc=trcmin., tck=tckmin.
Ouputs open, Burst Length = 4, CL=3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
PRECHARGE STANDBY CURRENT in tck = min.
Power Down Mode
Symb.
ICC1
-8/-8A -8B
max.
x4 210
165
x8 210
165
x16 210
165
ICC2P
2
2
CS =VIH (min.), CKE<=Vil(max)
PRECHARGE STANDBY CURRENT in tck = min.
Non-Power Down Mode
ICC2N
19
16
CS = VIH (min.), CKE>=Vih(min)
NO OPERATING CURRENT
tck = min., CS = VIH(min),
active state ( max. 4 banks)
CKE>=VIH(min.) ICC3N
45
40
CKE<=VIL(max.) ICC3P
10
10
BURST OPERATING CURRENT
tck = min.,
Read command cycling
AUTO REFRESH CURRENT
tck = min.,
Auto Refresh command cycling
SELF REFRESH CURRENT
Self Refresh Mode, CKE=0.2V
ICC4
x4 210
165
x8 210
165
x16 210
165
ICC5
240
195
standard version ICC6
2.5
2.5
Note
mA 3
mA
mA
mA 3
mA 3
mA 3
mA 3
mA 3,4
mA
mA
mA 3
mA 3
Notes:
3. These parameters depend on the cycle rate. These values are measured at 125 MHz for -8 & -8A
and at 100 MHz for -10 parts. Input signals are changed once during tck, excepts for ICC6 and for standby
currents when tck=infinity.
4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3
and BL=4 is assumed and the VDDQ current is excluded.
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