HYB39S256160T-8B 查看數據表（PDF） - Infineon Technologies

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HYB39S256160T-8B

256 MBit Synchronous DRAM

Infineon Technologies 

HYB39S256400/800/160T

256MBit Synchronous DRAM

Parameter

Symbol

Limit Values

Unit

Activate(a) to Activate(b) Command tRRD

period

CAS(a) to CAS(b) Command period tCCD

-8

PC100-

222

-8A

PC100-

322

-8B

PC100-

323

min. max. min. max. min. max.

16 – 16

20 – ns 5

1 – 1 – 1 – CLK

Refresh Cycle

Refresh Period (8192 cycles)

Self Refresh Exit Time

tREF

tSREX

– 64 – 64 – 64 ms

10

10

10

ns

Read Cycle

Data Out Hold Time

Data Out to Low Impedance Time

Data Out to High Impedance Time

DQM Data Out Disable Latency

tOH

3 – 3 – 3 – ns 2

tLZ

0 – 0 – 0 – ns

tHZ

3 8 3 8 3 10 ns

tDQZ

– 2 – 2 – 2 CLK

Write Cycle

Data Input to Precharge

(write recovery)

DQM Write Mask Latency

tWR

2 – 2 – 2 – CLK

tDQW

0 – 0 – 0 – CLK

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