AM29LV081B 查看數據表（PDF） - Advanced Micro Devices

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AM29LV081B

8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory

Advanced Micro Devices 

DATA SHEET

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. Table 1 lists the device bus operations, the

inputs and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29LV081B Device Bus Operations

Operation

CE#

OE# WE# RESET# Addresses (Note 1) DQ0–DQ7

Read

Write

Standby

Output Disable

L

L

H

H

AIN

L

H

L

H

AIN

VCC ±

0.3 V

X

X

VCC ±

0.3 V

X

L

H

H

H

X

DOUT

DIN

High-Z

High-Z

Reset

X

X

X

L

X

High-Z

Sector Protect (Note 2)

L

H

L

VID

Sector Address, A6 = L,

A1 = H, A0 = L

X

Sector Unprotect (Note 2)

L

H

L

VID

Sector Address, A6 = H,

A1 = H, A0 = L

X

Temporary Sector Unprotect

X

X

X

VID

X

X

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A19–A0.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE# should

remain at VIH.

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs pro-

duce valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. ICC1 in

the DC Characteristics table represents the active cur-

rent specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the Un-

lock Bypass mode, only two write cycles are required to

program a byte, instead of four. The “Byte Program

Command Sequence” section has details on program-

ming data to the device using both standard and Unlock

Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicate the address

space that each sector occupies. A “sector address”

consists of the address bits required to uniquely select

a sector. The “Command Definitions” section has de-

tails on erasing a sector or the entire chip, or suspend-

ing/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

21525D6 October 12, 2006

Am29LV081B

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