AM52-0001 查看數據表（PDF） - Tyco Electronics
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AM52-0001 Datasheet PDF : 6 Pages
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1.2 W High Efficiency Power Amplifier
Absolute Maximum Ratings 1
Parameter
Absolute Maximum
Input Power 2
Operating Voltage 2
+23 dBm
VDD = + 10 Volts
Junction Temperature 3
VGG = - 6 Volts
+150 °C
Storage Temperature
-65 °C to +150 °C
Operating Temperature -40 °C to +85 °C
1. Exceeding any one or combination of these limits may cause
permanent damage.
2. Ambient Temperature (TA) = + 25°C
3. See temperature derating curve.
Functional Block Diagram
(AMPS 824-849 MHz)
AM52-0001
V1.00
C7
VG1
R F IN
C10
C3
1
2
3
VD1
4
C6
C1
9
C2
8
T1
7
T2
C11
VD2
C9
6
RF OUT
C8
5
VG2
C4
C5
Pin Configuration
Pin No.
1
2
3
4
5
6
7
8
9
Pin Name
VG1
RF IN
GND
VD1
VG2
GND
RF OUT
VD2
Puck
Description
Negative supply voltage, First stage
RF Input of the amplifier
DC and RF Ground
Positive supply voltage, First stage
Negative supply voltage, First stage
DC and RF Ground
RF Output of the amplifier
Positive supply voltage, Second stage
DC and RF Ground
Recommended PCB Configuration
Layout View (AMPS 824-849 MHz)
External Circuitry Parts List
(AMPS 824-849 MHz)
Part
Value
Purpose
C1 - C3
220 pF
By-Pass
C4 - C7
0.1 uF
By-Pass
C8
8 pF
Power Tuning
C9, C10
56 pF
DC Block
C11
1.0 uF
By-Pass
T1
0.470”
Matching Transmission
T2
0.250”
Lines (50 Ω)
1.) The recommended layout is specifically for the AMPS application. It
shows EIA code size 0603 standard SMT capacitors with the exception of
C11 which is a EIA code size 3528
2.) The location of C9, C10 and C11 is not critical to the performance of
the amplifier.
Cross Section View
C11
C7
C2
C3
0.47" (T1)
C10
C6
C1
C4
C5
0.25" (T2)
C8
C9
RF Traces + Components
RF Ground
DC Routing
Customer Defined
The PCB dielectric between RF traces and RF ground layers should
be chosen to reduce RF discontinuities between 50 Ω lines and
package pins. M/A-COM recommends an FR-4 dielectric thickness
of 0.008”(0.2 mm) yielding a 50 Ω line width of 0.015”(0.38 mm).
The recommended metalization thickness is 1 oz. copper and ground
metalization thickness is 2 oz.. Shaded traces are vias to DC
Routing layer and traces on DC Routing layer.
Biasing Procedure
The AM52-0001 requires that VGG bias be applied prior to ANY
VDD bias. Permanent damage will occur if this procedure is not
followed. All FETs in the PA will draw IDSS and damage internal
circuitry. Resistance added in seiries with Vg1 and Vg2 may degrade
performance.
Specifications Subject to Change Without Notice.
2
North America: Tel. (800) 366-2266 ♦ Asia/Pacific: Tel. +81 3 3226-8761 ♦ Europe:
Fax (800) 618-8883
Fax +81 3 3226-8769
M/A-COM Inc.
Tel. +44 (1344) 869-595
Fax +44 (1344) 300 020
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