AD8110AST 查看數據表（PDF） - Analog Devices

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AD8110AST

260 MHz, 16 x 8 Buffered Video Crosspoint Switches

Analog Devices 

TIMING CHARACTERISTICS (Serial)

Parameter

Serial Data Setup Time

CLK Pulsewidth

Serial Data Hold Time

CLK Pulse Separation, Serial Mode

CLK to UPDATE Delay

UPDATE Pulsewidth

CLK to DATA OUT Valid, Serial Mode

Propagation Delay, UPDATE to Switch On or Off

Data Load Time, CLK = 5 MHz, Serial Mode

CLK, UPDATE Rise and Fall Times

RESET Time

Symbol

Min

t1

20

t2

100

t3

20

t4

100

t5

0

t6

50

t7

–

–

–

–

200

AD8110/AD8111

Limit

Typ

Max

180

8

8

100

Units

ns

ns

ns

ns

ns

ns

ns

ns

µs

ns

ns

1

CLK

0

1

DATA IN

0

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

t2

t1

t3

OUT7 (D4)

t7

t4

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

OUT7 (D3)

OUT00 (D0)

t5

t6

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

Figure 1. Timing Diagram, Serial Mode

VIH

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

2.0 V min

Table I. Logic Levels

VIL

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

VOH

DATA OUT

VOL

DATA OUT

IIH

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

0.8 V max

2.7 V min

0.5 V max

20 µA max

IIL

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

–400 µA min

IOH

DATA OUT

–400 µA max

IOL

DATA OUT

3.0 mA min

REV. 0

–3–

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