M5M5255DP-45LL 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M5255DP-45LL Datasheet PDF : 7 Pages
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'97.4.7
MITSUBISHI LSIs
M5M5255DP,FP -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc=5V±10%, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level···················VIH=2.4V,VIL=0.6V
Vcc
Input rise and fall time··········5ns
1.8kΩ
Reference level····················VOH=VOL=1.5V
Output loads·························Fig.1,CL=30pF (-45LL,-45XL )
CL=50pF (-55LL,-55XL )
CL=100pF (-70LL,-70XL )
DQ
(Including
scope and JIG)
990Ω CL
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
tCR
ta(A)
ta(S1)
ta(S2)
tdis(S1)
tdis(S2)
ten(S1)
ten(S2)
tV(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output disable time after /S1 high
Output disable time after S2 low
Output enable time after /S1 low
Output enable time after S2 high
Data valid time after address
Limits
-45LL, XL -55LL, XL -70LL, XL Unit
Min Max Min Max Mi Max
45
55
70
ns
45
55
70 ns
45
55
70 ns
45
55
70 ns
15
20
25 ns
15
20
25 ns
5
5
5
ns
5
5
5
ns
10
10
10
ns
(3) WRITE CYCLE
Limits
Symbol
Parameter
-45LL, XL -55LL, XL -70LL, XL Unit
Min Max Min Max Min Max
tCW
Write cycle time
45
55
70
ns
tw(W) Write pulse width
35
40
50
ns
tsu(A) Address setup time
0
0
0
ns
tsu(A-WH) Address setup time with respect to /W 40
50
65
ns
tsu(S1) Chip select 1 setup time
40
50
65
ns
tsu(S2) Chip select 2 setup time
40
50
65
ns
tsu(D) Data setup time
20
25
30
ns
th(D)
trec(W)
Data hold time
Write recovery time
0
0
0
ns
0
0
0
ns
tdis(W) Output disable time from /W low
ten(W) Output enable time from /W high
15
5
20
5
25 ns
5
ns
MITSUBISHI
ELECTRIC
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