M5M5255DP-45LL 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M5255DP-45LL Datasheet PDF : 7 Pages
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'97.4.7
(4) TIMING DIAGRAMS
Read cycle
A0~14
/S1
S2
DQ1~8
/W = "H" level
(Note 3)
(Note 3)
MITSUBISHI LSIs
M5M5255DP,FP -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
tCR
ta(A)
ta (S1)
ta (S2)
ten (S1)
ten (S2)
tv (A)
tdis (S1)
tdis (S2)
DATA VALID
(Note 3)
(Note 3)
Write cycle (/W control mode)
tCW
A0~14
/S1
S2
/W
DQ1~8
(Note 3)
(Note 3)
tsu (S1)
tsu (S2)
tsu (A-WH)
tsu (A)
tw (W)
trec (W)
tdis (W)
ten (W)
DATA IN
STABLE
tsu (D) th (D)
(Note 3)
(Note 3)
MITSUBISHI
ELECTRIC
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