M5M5255DP-45LL 查看數據表（PDF） - MITSUBISHI ELECTRIC
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M5M5255DP-45LL Datasheet PDF : 7 Pages
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'97.4.7
MITSUBISHI LSIs
M5M5255DP,FP -45LL,-55LL,-70LL,
-45XL,-55XL,-70XL
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S1 control mode)
tCW
A0~14
tsu (A)
tsu (S1)
trec (W)
/S1
S2
(Note 3)
(Note 5)
/W
(Note 3)
DQ1~8
Write cycle (S2 control mode)
A0~14
(Note 4)
tsu (D)
th (D)
DATA IN
STABLE
tCW
(Note 3)
(Note 3)
/S1
S2
/W
DQ1~8
(Note 3)
tsu (A)
tsu (S2)
trec (W)
(Note 5)
(Note 3)
(Note 4)
tsu (D)
th (D)
DATA IN
STABLE
(Note 3)
(Note 3)
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed while S2 high overlaps /S1 and /W low.
5 : When the falling edge of /W is simultaneously or prior to the falling edge of /S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6 : Don't apply inverted phase signal externally when DQ pin is output mode.
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ELECTRIC
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