AMMC-6222-W50 查看數據表（PDF） - Avago Technologies
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AMMC-6222-W50 Datasheet PDF : 12 Pages
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AMMC-6222 Application and Usage
To VDD DC supply
>= 100 pF Capacitor
RF INPUT
VD1
VD2
AMMC-6222
Open
RF OUTPUT
Gold Plated Shim (Optional)
Figure 19. Low Current, Low Output Power State
>= 100 pF Capacitor
To VDD DC supply
RF INPUT
VD1
VD2
AMMC-6222
RF OUTPUT
Gold Plated Shim (Optional)
Figure 20. High Current, High Output Power State
Biasing and Operation
The AMMC-6222 is normally biased with a positive drain
supply connected to the VD1 and VD2 pads through
bypass capacitor as shown in Figures 19 and 20. The
recommended drain supply voltage for general usage is
4V and the corresponding drain current is approximately
120mA. It is important to have at least 100pF bypass
capacitor and the capacitor should be placed as close
to the component as possible. Aspects of the amplifier
performance may be improved over a narrower
bandwidth by application of additional conjugate,
linearity, or low noise (Topt) matching.
For receiver front end low noise applications where high
power and linearity are not often required, the AMMC-
6222 can be set in low current state when SELECT pad
is open as shown in Figure 19. In this configuration, the
bias current is approximately 85mA, 95mA and 105mA
for 3V, 4V and 5V respectively.
In applications where high output power and linearity
are often required such as LO or transmitter drivers, the
AMMC-6222 can be selected to operate at its highest
output power by grounding SELECT pad as shown in
Figure 20. At 5V, the amplifier can provide Psat of about
20dBm. The bias current in this configuration is 115mA,
120mA and 125mA for 3V, 4V and 5V respectively.
In both cases, bonding wires at the input and output in
the range of 0.15nH would likely improve the overall Noise
Figure and input, output match at most frequencies.
No ground wires are needed because all ground
connections are made with plated through-holes to the
backside of the substrate.
Refer the Absolute Maximum Ratings table for allowed
DC and thermal condition.
Figure 21. Simplified High Linearity LNA Schematic
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