AN-9033 查看數據表（PDF） - Fairchild Semiconductor
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AN-9033 Datasheet PDF : 8 Pages
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External Connection
Signal
1
Interface 1
(J1)
2
3
4
5
6
7
8
9
10
Signal
1
Interface 2
(CN1)
2
3
4
5
6
7
8
9
10
11
Power
P
Connection
N
U
V
W
High-Side Input Signal from CPU (Phase U)
High-Side Input Signal from CPU (Phase V)
High-Side Input Signal from CPU (Phase W)
Low-Side Input Signal from CPU (Phase U)
Low-Side Input Signal from CPU (Phase V)
Low-Side Input Signal from CPU (Phase W)
No connection
Fault-Out Signal to CPU
Bias Supply (+5V) Terminal for Photo coupler Primary Side Driving
Bias Supply GroundTerminal for Photo coupler Primary Side Driving
SPM Bias Supply +15V Terminal for High_Side (Phase W)
SPM Bias Supply Ground Terminal for High_Side (Phase W)
No Connection
SPM Bias Supply +15V Terminal High_Side (Phase V)
SPM Bias Supply Ground Terminal High_Side (Phase V)
No Connection
SPM Bias Supply +15V Terminal for High_Side (Phase U)
SPM Bias Supply Ground Terminal for High_Side (Phase U)
No Connection
SPM Bias Supply +15V Terminal
SPM Bias Supply Ground Terminal
Positive DC Link Input Connection
Negative DC Link Input Connection
Motor Input Connection (Phase U)
Motor Input Connection (Phase V)
Motor Input Connection (Phase W)
©2003 Fairchild Semiconductor Corporation
4
Rev. A, May 2003
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