GTL2002D 查看數據表（PDF） - Philips Electronics
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GTL2002D Datasheet PDF : 24 Pages
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All the devices operate exactly the same and vary only on the number of I/O available. Any matched set of Sn and Dn
pins can be used as SREF and DREF (e.g., pin 12 and 13 on the GTL2010 can be used for SREF and DREF instead of
pins 2 and 23 which revert to S10 and D10).
Ordering Information
Package
SO
SSOP
TSSOP
VSSOP
HVQFN
Container
Tube
T&R
Tube
T&R
Tube
T&R
T&R
T&R
GTL2000
GTL2000DL
GTL2000DL-T
GTL2000DGG
GTL2000DGG-T
-
-
GTL2002
GTL2002D
GTL2002D-T
-
-
-
GTL2002DP-T
GTL2002DC-T
-
GTL2010
-
-
-
-
GTL2010PW
GTL2010PW -T
GTL2010BS-T
Table 2. GTL20xx Ordering Information
Data Sheets and IBIS Models
Data sheets and IBIS models can be downloaded from www.philipslogic.com
TECHNICAL INFORMATION
Block Diagram
GTL-TVC voltage-limiting application
In voltage-limiting applications, the common GREF input must be connected to one side (Sn or Dn) of any of the
transistors (see Figure 6). This connection determines the DREF input of the reference transistor. The DREF and GREF
inputs are connected together through a pull up resistor (typically 200 kΩ) to the VDD supply. A filter capacitor (typically
0.1 µF) on DREF is recommended. Associated with the 200 kΩ resistor, the RC time constant is equal to 20 ms. The
larger the capacitor, the less the gate node will move, the slower it will rise on power up.
The opposite side of the reference transistor is used as the reference voltage SREF connection. The SREF input should
be less than VDD – 1.5 V to insure that the reference transistor is properly biased into conduction. If the SREF is set to
less than 1.5 V below Vdd, the maximum pass voltage may be less than the SREF voltage because the threshold voltage
(the minimum gate to source voltage necessary for conduction) may be limiting the pass voltage rather than the SREF
voltage. The gate to source threshold voltage will vary from part to part but will not vary within a package. The reference
transistor regulates the gate voltage (GREF) of all the pass transistors in the package when properly biased, as described
above.
1.8 V
1.5 V
1.2 V
1.0 V
VCORE
CPU
200 kΩ
GTL2002
GND GREF
SREF DREF
S1 D1
S2 D2
5V
VDD
Device
0.1 µF
7
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