AN8029 查看數據表（PDF） - Panasonic Corporation
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AN8029
Panasonic Corporation
AN8029 Datasheet PDF : 13 Pages
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Voltage Regulators
AN8029
s Application Notes (continued)
[1] Operation descriptions (continued)
8. Timer latch (continued)
VO
Power supply
output voltage
0
IDS
Power MOSFET
current
0
Power supply stop
Time
Power supply stop
Time
VOVP
TIM/OVP
terminal voltage
0
Power supply stop
OVP
VTH = 7.3 V (typ.)
Time
Figure 10. Timer latch basic operation
9. Output block
In order to drive the power MOSFET which is a capacitive load at high speed, this IC is adopting the totem pole
(push-pull) type output circuit which performs the sink and source of the current with the NPN transistor as shown
in figure 10.
The maximum sink/source current is ± 0.1 A (DC) and the current at peak is ±1.0 A (Peak). The circuit is
provided with the sink capability even if the supply voltage VCC is under the stop voltage so that it turns off the
power MOSFET without fail.
The peak current capability is mainly required and a particularly too large current is not required constantly.
Because the power MOSFET becomes a capacitive load for the output, a large peak current is required for driving
it at a high speed. However, after the charge and discharge, a particularly large current is not required to keep such
condition. In the case of this IC, the peak current capability of ±1 A is ensured by taking a capacitance value of
the power MOSFET used into account.
The parasitic LC of the power MOSFET may
produce ringing to decrease the output pin under
the GND potential. When the voltage decrease of
the output pin becomes larger than the voltage drop
of diode and its voltage becomes negative, the
parasitic diode consisting of the substrate and
collector of the output NPN turns on. This phe-
Schottky barrier
diode
nomenon can cause the malfunction of device. In
such a case, the Schottky barrier diode should be
connected between the output and GND.
Figure 11
11
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