AOZ1016 查看數據表（PDF） - Alpha and Omega Semiconductor
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AOZ1016 Datasheet PDF : 15 Pages
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AOZ1016
In a buck converter, output capacitor current is continuous.
The RMS current of the output capacitor is decided by
the peak to peak inductor ripple current. It can be
calculated by:
I CO_RMS = -∆----I---L--
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
Loop Compensation
The AOZ1016 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
f P1
=
-----------------1------------------
2π × CO × RL
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
------------------------1-------------------------
2π × CO × ESRCO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
The compensation design is actually to shape the
converter close loop transfer function to get the desired
gain and phase. Several different types of compensation
network can be used for the AOZ1016. In most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
The FB pin and the COMP pin are the inverting input
and the output of internal transconductance error ampli-
fier. A series R and C compensation network connected
to COMP provides one pole and one zero. The pole is:
f P2
=
----------------G-----E----A------------------
2π × CC × GVEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is compensation capacitor.
The zero given by the external compensation network,
capacitor CC (C5 in Figure 1) and resistor RC (R1 in
Figure 1), is located at:
fZ2
=
-----------------1-------------------
2π × CC × RC
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The
system crossover frequency is where the control loop has
unity gain. The crossover frequency is also called the
converter bandwidth. Generally, a higher bandwidth
means faster response to load transient. However,
the bandwidth should not be too high due to system
stability concern. When designing the compensation
loop, converter stability under all line and load conditions
must be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of the switching frequency. The AOZ1016
operates at a fixed switching frequency range from
350kHz to 600kHz. It is recommended to choose a
crossover frequency less than 30kHz.
f C = 30kHz
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
RC
=
f
C
×
--V-----O----
V FB
×
-----2---π-----×-----C-----O------
GEA × GCS
where;
fC is the desired crossover frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V.
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. CC can is selected by:
CC
=
---------------1---.--5-----------------
2π × RC × f P1
Rev. 1.1 September 2007
www.aosmd.com
Page 10 of 15
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