24LLC02TS8 查看數據表（PDF） - CERAMATE TECHNICAL

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24LLC02TS8

2K-bit Serial EEPROM for Low Power

CERAMATE TECHNICAL 

24LLC02

2K-bit Serial EEPROM for Low Power

Master

SCL Line

Bit 1

Data from

Transmitter

ACK from

Receiver

Bit 9

ACK

Figure 1-8. Acknowledge Response From Receiver

• Slave Address : After the master initiates a Start condition, it must output the address of the device to be

accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier

for the 24LLC02 is “1010B”. The next three bits comprise the address of a specific device. The device

address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade

up to eight 24LLC02 on the bus (see Table 1-2 below).are used by the master to select which of the blocks

of internal memory (1 block= 256 words) are to be accessed. The bits are in effect the most significant bits

of the word address.

• Read/Write : The final (eighth) bit of the slave address defines the type of operation to be performed. If the

R /W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.

Device

24LLC02

Table 1-2. Slave Device Addressing

Device Identifier

Device Address

b7 b6 b5 b4

b3

b2

b1

1010

A2

A1

A0

NOTE: The B2, B1, B0 correspond to the MSB of the memory array address word.

R/ W Bit

b0

R/ W

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C

Tel:886-3-3529445

Fax:886 -3 -3521052

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Rev 1.2 May 6,2002

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