APW7063 查看數據表（PDF） - Anpec Electronics

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APW7063

Synchronous Buck PWM and Linear Controller

Anpec Electronics 

APW7063

Functional Pin Description (Cont.)

COMP (Pin 5)

PGND (Pin 10)

This pin is t he output of t he error amplifier. Add an

external resis tor and capacitor network to provide the

loop compens ation for t he P W M c onvert er (see

A pplic at ion Information).

Power ground for t he gate diver. Connect t he lower

MOSFET source to this pin.

LGATE (Pin 11)

Pull this pin below 0.4V will shutdown the controller,

forcing the UGATE and LGATE signals to be 0V. A soft

start cycle will be initiated upon the release of this pin.

GND (Pin 6)

Signal ground for the IC.

PHASE (Pin 7)

A resistor (ROCSET) is connected bet ween this pin and

the drain of the low-side MOSFET will determine the

over current limit. An internally generated 250uA current

source will flow through this resistor, creating a voltage

drop. This voltage will be compared with the voltage

ac ross the low-side MOSFET. The threshold of t he

over current limit is therefore given by :

R OCSET

= ILIMIT × R DS(ON)

250uA

This pin provides the gate drive signal for the low side

MOSFET.

VCC (Pin 12)

This pin provides a supply voltage for the device, when

VCC is above the rising threshold 4.2V, It turns on the

device is turned on, and conversely, VCC is below the

falling threshold 3.9V, the device is turned off. A 1uF

decoupling capacitor to GND is recommended.

DRIVE (Pin 13)

Connect this pin to the gate of an external N-channel

MOS FET transis tor. This pin provides the gate volt-

age for the linear regulator pass transistor. It also pro-

vides a means of compensating the linear controller

for applications where the user needs to optimize the

regulator transient response.

An over current condit ion will c yc le t he s oft st art

func tion unt il the over current condition is removed.

Because of the comparator delay time, so the on time

of the low-side MOSFET must be longer than 800ns to

have the over current protection work.

FBL (Pin 14)

Connec t this pin to the out put of the linear regulator

via a proper s ized resistor divider. The voltage at this

pin is regulat ed to 0.8V and the output voltage is de-

termined using the following formula :

UGATE (Pin 8)

This pin provides gate drive for the high-side MOSFET.

BOOT (Pin 9)

This pin provides the supply voltage to the high side

MOS FE T driver. For driving logic level N-channel

MOSEFT, a boots trap circuit can be use to create a

suitable driver’s supply.

VOUT

=

0.8V

×

1

+

ROUT

RGND



where ROUT is the resistor connected from VOUT to FBL,

and RGND is the resistor connected from FBL to GND.

This pin also monitores the under-voltage events, if

the linear regulator is not used, tie the FBL to VREG.

C opyright © ANPEC Electronics C orp.

7

Rev. A.7 - Nov., 2005

www.anpec.com.tw

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