AS1329 查看數據表（PDF） - austriamicrosystems AG
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AS1329 Datasheet PDF : 17 Pages
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AS1329
Data Sheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
SW 1
6 VIN
GND 2 AS1329 5 VOUT
FB 3
4 SHDNN
Pin Descriptions
Table 2. Pin Descriptions
Pin
Name
SW
GND
FB
SHDNN
VOUT
VIN
Pin
Number
1
2
3
4
5
6
Description
Switch Pin. Connect an inductor between this pin and VIN. Keep the PCB
trace lengths as short and wide as is practical to reduce EMI and voltage
overshoot. If the inductor current falls to zero, or pin SHDNN is low, an
internal 100Ω anti-ringing switch is connected from this pin to VIN to
minimize EMI.
Note: An optional Schottky diode can be connected between this pin and
VOUT.
Signal and Power Ground. Provide a short, direct PCB path between this
pin and the negative side of the output capacitor(s).
Feedback Pin. Feedback input to the gm error amplifier. Connect a resistor
divider tap to this pin. The output voltage can be adjusted from 2.5 to 5V by:
VOUT = 1.23V[1 + (R1/R2)]
Shutdown Pin. Logic controlled shutdown input.
1 = Normal operation, 1.2MHz typical operating frequency.
0 = Shutdown; quiescent current <1µA. If SHDNN is undefined, pin SW may
ring.
Note: In a typical application, SHDNN should be connected to VIN through a
1MΩ pull-up resistor.
Output Voltage Sense Input and Drain of the Internal PMOS
Synchronous Rectifier. Bias is derived from VOUT when VOUT exceeds VIN.
PCB trace length from VOUT to the output filter capacitor(s) should be as
short and wide as is practical.
Input Voltage. The AS1329 gets its start-up bias from VIN unless VOUT
exceeds VIN, in which case the bias is derived from VOUT. Thus, once
started, operation is completely independent from VIN. Operation is only
limited by the output power level and the internal series resistance of the
supply.
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