AS1505 查看數據表（PDF） - austriamicrosystems AG

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AS1505

Octal 8-Bit Programmable Low-Power DACs with Shutdown and Mid-Scale Reset

austriamicrosystems AG 

AS1504, AS1505

Data Sheet

austriamicrosystems

DAC Outputs

DAC Outputs

The 8 DAC outputs (OUT1:OUT8) present a constant output resistance of approximately 5kΩ independent of code set-

tings. The distribution of ROUT from DAC to DAC typically matches within ±1%. Device-to-device matching is process-

lot dependent with a ±20% variation. The change in ROUT with temperature has a 500 ppm/°C temperature coefficient.

Note: During shutdown the OUTx outputs are open-circuited.

Serial Interface

The AS1504/AS1505 are controlled via a standard three-wire serial input. The three input pins are CLK, CSN and SDI.

The positive-edge sensitive CLK input requires a clean transition to avoid clocking spurious data into the serial input

register (standard logic families are perfectly adequate). If mechanical switches are used for device evaluation, they

should be de-bounced by a flip-flop or other suitable means.

Figure 11 on page 8 shows details of the internal digital circuitry. When CSN is pulled low, the clock can load data into

the serial register on each positive clock edge (see Table 7).

Table 7. Function of Pins CSN and CLK

CSN

CLK

Register Activity

1

X

No effect.

0

Positive Edge Shifts serial register one bit loading the next bit in from the SDI pin.

Data is transferred from the serial register to the decoded DAC register (see Figure

Positive Edge

X

16).

The data setup and data hold times in Table 3 on page 3 determine the valid data time requirements. The last 11 bits of

the data word entered into the serial register are held when CSN goes high. When CSN goes high it gates the address

decoder which enables one of the eight positive-edge triggered DAC registers (see Figure 16).

Figure 16. Equivalent Control Logic

AS1504/

AS1505

CSN

Address

Decode

DAC1

DAC2

DAC8

Serial

CLK

Register

SDI

The target DAC register is loaded with the last eight bits of the serial data word completing one DAC update. To

change all eight output settings, eight separate 11-bit data words must be clocked in to the device.

Note: All digital inputs (CSN, SDI, RSN, SHDNN, and CLK) are protected with the series input resistor and parallel

zener diode ESD circuit illustrated in Figure 17.

Figure 17. Equivalent ESD Protection Circuit

50Ω

Logic

Note: Digital inputs can be driven by voltages exceeding VDD thus providing logic level translation from 5V logic when

the device is operated from a 3V supply.

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