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AS1747-BTDT(2009) 查看數據表(PDF) - austriamicrosystems AG

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AS1747-BTDT Datasheet PDF : 13 Pages
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AS1747
Datasheet - Timing Diagrams
10 Timing Diagrams
Figure 15. Switching Time
VN_
Logic
Input
NO_
OR NC_
IN_
GND
VCC
VCC
COM_
VOUT
RL
CL
CL includes fixture and stray capacitance
VOUT = VN_(RL / (RL + RON))
Logic VCC
Input 0V
Switch 0V
Output
50%
tr < 5ns
tf < 5ns
tOFF
VOUT 0.9 x VOUT
0.9 x VOUT
IN depends on switch configuration;
Input polarity determined by sense of switch.
tON
Figure 16. Break-Before-Make Interval
VCC
VN_
Logic
Input
NC_
NO_
IN_
VCC
COM_
VOUT
VCC
Logic
Input
0V
RL
CL
GND
CL includes fixture and stray capacitance
VOUT
50%
tBBM
0.9 x VOUT
Figure 17. Charge Injection
RGEN
+
VGEN
NC_
OR NO_
GND
VCC
VCC
COM_
IN_
VIL to VIH
ΔVOUT
VOUT
VOUT
CL
IN OFF
IN OFF
ON
ON
Q = (ΔVOUT)(CL)
OFF
OFF
Logic input waveforms inverted for switches
that have the opposite logic sense.
www.austriamicrosystems.com
Revision 1.01
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