AS6C62256 查看數據表（PDF） - Alliance Semiconductor
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AS6C62256 Datasheet PDF : 12 Pages
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February 2007
AS6C62256
®
32K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL
TEST CONDITION
Supply Voltage
Input High Voltage
Input Low Voltage
VCC
VIH*1
VIL*2
Input Leakage Current
ILI VCC ≧ VIN ≧ VSS
Output Leakage
Current
ILO
VCC ≧ VOUT ≧ VSS,
Output Disabled
Output High Voltage
VOH IOH = -1mA
Output Low Voltage
VOL IOL = 2mA
MIN.
2.7
0.7*Vcc
- 0.5
-1
-1
2.4
-
Average Operating
ICC
Cycle time = Min.
CE# = VIL , II/O = 0mA
-55
-
Power supply Current
Cycle time = 1µs
ICC1 CE#≦0.2V and II/O = 0mA
-
other pins at 0.2V or VCC-0.2V
Standby Power
Supply Current
ISB CE# = VIH
ISB1
CE# ≧VCC - 0.2V
-C
-I
-
-
-
Notes: C = Commercial Temperature I = Industrial Temperature
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. 10µA for special request
5. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at VCC = VCC(TYP.) and TA = 25ºC
TYP. *5
3.3
-
-
-
-
3.0
-
MAX.
5.5
VCC+0.5
0.6
1
1
-
0.4
15
45
3
10
1
3
1
50*4
1
80*4
UNIT
V
V
V
µA
µA
V
V
mA
.
mA
mA
µA
µA
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
SYMBOL
MIN.
Input Capacitance
CIN
-
Input/Output Capacitance
CI/O
-
Note : These parameters are guaranteed by device characterization, but not production tested.
MAX
6
8
UNIT
pF
pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 50pF + 1TTL, IOH/IOL = -1mA/2mA
02/FEB/07, v1.0
Alliance Memory Inc.
Page 3 of 12
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