AS7C1024B 查看數據表（PDF） - Alliance Semiconductor
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AS7C1024B Datasheet PDF : 9 Pages
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AS7C1024B
®
Write waveform 2 (CE1 and CE2 controlled)10,11,12
Address
CE1
CE2
WE
DIN
DOUT
tWC
tAW
tAH
tWR
tAS
tCW1, tCW2
tWP
tWZ
tDW
tDH
Data valid
AC test conditions
– Output load: see Figure B.
– Input pulse level: GND to 3.5V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
+5V
+3.5V 90%
90%
10%
GND
2 ns
10%
Figure A: Input pulse
DOUT
255Ω
480Ω
C13
GND
Figure B: 5V Output load
Thevenin equivalent:
168Ω
DOUT
+1.728V
Notes
1 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
2 This parameter is sampled and not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4 tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6 WE is high for read cycle.
7 CE1 and OE are low and CE2 is high for read cycle.
8 Address valid prior to or coincident with CE1 transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
3/26/04, v 1.2
Alliance Semiconductor
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