AS7C1026C 查看數據表（PDF） - Alliance Semiconductor
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AS7C1026C Datasheet PDF : 9 Pages
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AS7C1026C
®
Functional description
The AS7C1026C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-
performance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is
static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or
write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1026C is packaged in
common industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
Voltage on VCC relative to GND
Vt1
–0.50
+7.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.25
W
Storage temperature (plastic)
Tstg
–55
+125
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
50
mA
Note:
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
WE
OE
LB
H
X
X
X
L
H
L
L
L
H
L
H
L
H
L
L
L
L
X
L
L
L
X
L
L
L
X
H
L
H
H
X
L
X
X
H
Key: H = high, L = low, X = don’t care.
UB
I/O0–I/O7 I/O8–I/O15
Mode
X
High Z
High Z
Standby (ISB), ISBI)
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
DOUT
DOUT
Read I/O0–I/O15 (ICC)
L
DIN
DIN
Write I/O0–I/O15 (ICC)
H
DIN
High Z
Write I/O0–I/O7 (ICC)
L
High Z
DIN
Write I/O8–I/O15 (ICC)
X
H
High Z
High Z
Output disable (ICC)
12/5/06, v 1.0
Alliance Memory
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