AD8303 查看數據表（PDF） - Analog Devices
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AD8303 Datasheet PDF : 16 Pages
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AD8303
Table I. Control-Logic Truth Table
CS CLK RS MSB SHDN LDA/B Serial Shift Register Function
DAC Register Function
HX H X H
H
LL HX H
H
LH HX H
H
L ↑+ H X
H
H
↑+ L H X
H
H
HX H X H
↓–
HX H X H
L
XX L H H
X
X X ↑+ H H
H
XX L L
H
X
X X ↑+ X
H
H
XX X X L
X
No Effect
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Latched
Latched
Latched
Updated with Current Shift Register Contents
Transparent
Loaded with 800H
Latched with 800H
Loaded with All Zeros
Latched All Zeros
No Effect
NOTES
1↑+ positive logic transition; ↓– negative logic transition; X Don’t Care.
2Do not clock in serial data while LDA or LDB is LOW.
Pin No. Name
Function
PIN DESCRIPTIONS
1
AGND
Analog Ground.
2
VOUTA
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
3
VREF
Reference Voltage Output Terminal. Very high output resistance must be buffered if used as a virtual
ground.
4
DGND Digital Ground
5
CS
Chip Select, Active Low Input. Disables shift register loading when high. Does not effect LDA or LDB
operation.
6
CLK
Clock Input, positive edge clocks data into shift register.
7
SDI
Serial Data Input, input data loads directly into the shift register.
8
LDA
Load DAC register strobes, active low. Transfers shift register data to DAC A register. Asynchronous active
low input. See Control Logic Truth Table for operation.
9
RS
Resets DAC register to zero condition or half-scale depending on MSB pin. Asynchronous active low input.
10
LDB
Load DAC register strobes, active low. Transfers shift register data to DAC B register. Asynchronous active
low input. See Control Logic Truth Table for operation.
11
MSB
Digital Input: Logic High presets DAC registers to half-scale 800H (sets MSB bit to one) when the RS pin
is strobed; Logic Low clears all DAC registers to zero (000H) when the RS pin is strobed.
12
SHDN
Active low shutdown control input. Does not affect register contents as long as power is present on VDD.
13
VDD
Positive power supply input. Specified range of operation +2.7 V to +5.5 V
14
VOUTB
DAC voltage output, 2.0475 V full scale with 0.5 mV per bit. An internal temperature stabilized reference
maintains a fixed full-scale voltage independent of time, temperature and power supply variations.
PIN CONFIGURATION
14-Pin P-DIP (N-14)
14-Lead SOIC (R-14)
AGND 1
14 VOUTB
VOUTA 2
13 VDD
VREF 3 AD8303 12 SHDN
DGND 4 TOP VIEW 11 MSB
(Not to Scale)
CS 5
10 LDB
CLK 6
9 RS
SDI 7
8 LDA
REV. 0
–5–
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