AS8ER128K32(2002) 查看數據表（PDF） - Austin Semiconductor
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AS8ER128K32 Datasheet PDF : 14 Pages
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Austin Semiconductor, Inc.
EEPROM
AS8ER128K32
WE\, CE\ Pin Operation
During a write cycle, address are latched by the falling edge
of WE\ or CE\, and data is latched by the rising edge of WE\
or CE\.
Write/Erase Endurance and Data Retention Time
The endurance is 104 cycles in case of the page programming
and 103 cycles in case of the byte programming (1% cumula-
tive failure rate). The data retention time is more than 10
years when a device is page-programmed less than 104 cycles.
RDY/Busy\ SIGNAL
RDY/Busy\ signal also allows status of the EEPROM to
be determined. The RDY/Busy\ signal has high impedance
except in write cycle and is lowered to VOL after the first write
signal. At the end of the write cycle, the RDY/Busy\ signal
changes state to high impedance. This allows many 58C1001
devices RDY/Busy\ signal lines to be wired-OR together.
PROGRAMMING/ERASE
The 58C1001 does NOT employ a BULK-erase function.
The memory cells can be programmed ‘0’ or ‘1’. A write cycle
performs the function of erase & write on every cycle with
the erase being transparent to the user. The internal erase data
state is considered to be ‘1’. To program the memory array
with background of ALL 0’s or All 1’s, the user would
program this data using the page mode write operation to
program all 1024 128-byte pages.
has a noise cancellation function that cuts noise if its width is
20ns or less in program mode.
Be careful not to allow noise of a width more than
20ns on the control pins. See Diagram 1 below.
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control
pins generated by external circuits (CPU, etc.) may act as a
trigger and turn the EEPROM to program mode by mistake.
To prevent this unintentional programming, the EEPROM must
be kept in an unprogrammable state while the CPR is in an
unstable state.
NOTE: The EEPROM should be kept in
unprogrammable state during VCC on/off by using CPU RE-
SET signal. See the timing diagram below.
DIAGRAM 1
Data Protection
1. Data Protection against Noise on Control Pins (CE\,
OE\, WE\) During Operation
During readout or standby, noise on the control pins
may act as a trigger and turn the EEPROM to programming
mode by mistake. To prevent this phenomenon, this device
DATA PROTECTION AT VCC ON/OFF
VCC
CPU
RESET
*Unprogrammable
*Unprogrammable
AS8ER128K32
Rev. 3.0 1/02
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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