AS8ER128K32 查看數據表（PDF） - Austin Semiconductor
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AS8ER128K32 Datasheet PDF : 18 Pages
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Austin Semiconductor, Inc.
EEPROM
AS8ER128K32
SOFTWARE DATA PROTECTION TIMING WAVEFORM (In non-protection mode)
VCC
CE\
tWC
Normal
active mode
WE\
Address
Data (each byte)
5555
AAAA
or
2AAA
5555 5555 AAAA 5555
or
2AAA
AA 55
80 AA 55
20
FUNCTIONAL DESCRIPTION
Automatic Page Write
Page-mode write feature allows 1 to 128 bytes of data to be
written into the EEPROM in a single write cycle. Following
the initial byte cycle, an additional 1 to 128 bytes can be writ-
ten in the same manner. Each additional byte load cycle must
be started within 30µs from the preceding falling edge of WE\
or CE\. When CE\ or WE\ is kept high for 100µs after data
input, the EEPROM enters write mode automatically and the
input data are written into the EEPROM.
DATA\ Polling
DATA\ polling allows the status of the EEPROM to be deter-
mined. If EEPROM is set to read mode during the write cycle,
an inversion of the last byte of data to be loaded outputs from
I/O's 7, 15, 23, and 31 to indicate that the EEPROM is per-
forming a write operation.
RDY/Busy\ Signal
RDY/Busy\ signal also allows status of the EEPROM to be
determined. The RDY/Busy\ signal has high impedance ex-
cept in write cycle and is lowered to VOL after the first write
signal. At the end of write cycle, the RDY/Busy\ signal changes
state to high impedance.
RES\ Signal
When RES\ is low, the EEPROM cannot be read or pro-
grammed. Therefore, data can be protected by keeping RES\
low when VCC is switched. RES\ should be high during read
and programming because it doesn't provide a latch function.
See timing diagram below.
RES\ Signal Diagram
VCC
RES\
Read inhibit
Program inhibit
Read inhibit
Program inhibit
AS8ER128K32
Rev. 5.3 6/05
10
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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