AS8SLC512K32 查看數據表（PDF） - Austin Semiconductor

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AS8SLC512K32

512K x 32 SRAM SRAM Memory Array MCM

Austin Semiconductor 

Austin Semiconductor, Inc.

CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)*

SYMBOL

PARAMETER

CADD

COE

CWE, CCS

CIO

A0 - A18 Capacitance

OE\ Capacitance

WE\ and CS\ Capacitance

I/O 0- I/O 31 Capacitance

NOTE:

*This parameter is sampled.

MAX

40

40

12

15

SRAM

AS8SLC512K32

UNITS

pF

pF

pF

pF

AC TEST CONDITIONS

TEST SPECIFICATIONS

Input pulse levels...........................................VSS to 3V

Input rise and fall times...........................................1ns/V

Input timing reference levels...............................1.5V

Output reference levels........................................1.5V

Output load..........................................See Figure 1, 2

RL = 50Ω

Q

ZO = 50Ω

30 pF

VL = 1.5V

FIGURE 1

Q

333Ω

3.3V

319Ω

5 pF

FIGURE 2

AS8SLC512K32

Rev. 2.5 5/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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