HI7133CPL 查看數據表（PDF） - Intersil

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HI7133CPL

3 1/2 Digit, Low Power, High CMRR, LCD/LED Display-Type A/D Converters

Intersil 

HI7131, HI7133

Design Information Summary Sheet

• OSCILLATOR FREQUENCY

fOSC ≈ 0.45/RC(OSC)

COSC ≥ 50pF

ROSC > 50kΩ

COSC = 50pF, ROSC = 180kΩ; fOSC (Typ) = 48kHz

• CLOCK FREQUENCY

fCLOCK = fOSC/4

• CLOCK PERIOD

tCLOCK = 1/fCLOCK

• CONVERSION CYCLE

TCYC = 4000 x tCLOCK = 16000 x tOSC

For fOSC = 40kHz; TCYC = 400ms

• SIGNAL INTEGRATION PERIOD

TINT = 1000 x tCLOCK

• 60/50Hz REJECTION CRITERIA

TINT / t60Hz or TINT / t50Hz = Integer

• OPTIMUM FULL SCALE ANALOG INPUT RANGE

VINFS = 200mV to 2V

• INPUTS VOLTAGE RANGE

(V- + 1V) < VIN LO or VIN HI < (V+ - 1V)

• MAXIMUM INTEGRATION CURRENT

IINT(MAX) = VINFS / RINT

Maximum integration current should be the maximum

buffer output current with no nonlinearity effect.

Maximum Buffer Output Current = 1µA

• INTEGRATOR MAXIMUM OUTPUT VOLTAGE SWING

VINT(MAX) = (TINT) (IINT(MAX))/CINT

(V- + 0.5) < VINT(MAX) < (V+ - 0.5)

(Typ) VINT(MAX) = 2V

• INTEGRATING RESISTOR

RINT = VINFS / IINT(MAX)

• INTEGRATING CAPACITOR

CINT = (TINT) (IINT(MAX)) / VINT(MAX)

• AUTO-ZERO CAPACITOR VALUE

REFERENCE CAPACITOR VALUE

0.1µF < CREF < 1µF

• REFERENCE INPUTS VOLTAGE RANGE

V- < VREFLO or VREFHI < V+

• REFERENCE VOLTAGE

VREF = VINFS/2

• COMMON PIN VOLTAGE

VCOMMON = V+ - 2.8, (Typ), VCOMMON is regulated and

can be used as a reference. It is biased between V+ and

V- and regulation is lost at (V+ -V-) < 6.8V. VCOMMON pin

does not have sink capability and can be externally pulled

down to lower voltages.

• DISPLAY TYPE

LCD, Non-Multiplexed

• POWER SUPPLY, V+ TO V-

Single +9V or 5V Nominal, +5V to +12V Functional

• DISPLAY READING

Reading = 1000 x (VIN / VREF)

Maximum Reading = 1999, for VIN = 1.999 x VREF

Typical Integrator Amplifier Output Waveform (INT Pin)

INTEGRATOR

VOLTAGE SWING

AUTO-ZERO PHASE

100 COUNTS OR

990 - 2990 COUNTS

SIGNAL INTEGRATE

PHASE FIXED

1000 COUNTS

DEINTEGRATE PHASE

0 - 2000 COUNTS

4000 COUNTS: TOTAL OF EACH CONVERSION CYCLE

NOTE: 1 Count = 1 Clock Cycle = 4 Oscillator Cycles.

ZERO INTEGRATE PHASE

10 COUNTS OR

900 COUNTS

3-1831

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